A verification method for dram controller

Abstract

The invention discloses a verification method used for a DRAM (Dynamic Random Access Memory) controller. The verification method comprises the following steps of: S1: according to a designed system scheme, initializing the DRAM controller; S2: through the DRAM controller, writing test data to a DRAM memory to carry out verification; and S3: after the verification is finished, reading the test data for comparison, verifying whether a verification result is qualified or not, and exiting the verification if the verification result is qualified; otherwise, executing the following steps of: S1) after a simulator finishes simulation for the DRAM controller, executing a time sequence information extraction script, and extracting DRAM clock working efficiency and the time sequence warning information of the DRAM from the output information of the simulator; and S2) aiming at the extracted time sequence information, executing a calculation script, judging whether practical DRAM clock working frequency meets a range allowed by the system scheme, entering S3) to execute an update verification script if an allowable time sequence margin is in the presence, and otherwise, entering S4) to execute a result notification script.

Description

technical field [0001] The invention relates to the field of chip logic verification, in particular to a verification method for a DRAM controller. Background technique [0002] Due to the complex working mechanism of DRAM, which involves the configuration and adjustment of many parameters, and the DRAM operates at a relatively high operating frequency, it has very high requirements for timing, so the verification of the DRAM controller is a very complicated task. In the current method, firstly, the controller is initialized, then the test data is written into the DRAM memory through the DRAM controller, and then the test data is read for comparison. When DRAM works, many timing parameters are involved. When a timing alarm occurs and the verification fails, at present, the verification personnel need to manually check the DRAM clock operating frequency and timing alarm information from the printed information, and then perform corresponding calculations. If If there is an a...

AI Technical Summary

Problems solved by technology

When DRAM works, many timing parameters are involved. When a timing alarm occurs and the verification fails, at present, the verification personnel need to manually check the DRAM clock operating frequency and timing alarm information from the printed information, and then perform corresponding calculations. If If there is an allowable timing margin, adjust the register configuration of the corresponding DRAM controller and restart the verification. If the allowable timing margin is exceeded, timing optimization needs to be performed from a design perspective. This manual method is inefficient. High and Accurate Questions

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