Temperature detection structure
A technology for detecting structures and interconnection structures, which is applied in the field of testing, can solve problems such as the large impact on the performance of three-dimensional packaging structures, and achieve the effects of simple methods that are beneficial to thermal monitoring and management.
Active Publication Date: 2019-02-12
SEMICON MFG INT (SHANGHAI) CORP
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Problems solved by technology
[0003] The three-dimensional packaging structure formed by using through-silicon vias integrates multiple chips with different functions, and the performance of the three-dimensional packaging structure during operation is greatly affected by temperature. However, how to thermally manage the three-dimensional packaging structure still faces a relatively large technical challenge. bottleneck
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[0032] An embodiment of the present invention provides a temperature detection structure, which uses a TSV interconnection structure to measure the temperature of a semiconductor substrate or a packaging structure in real time, which is beneficial to thermal monitoring and management of a chip or a packaging structure.
[0033] In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present invention in detail, for convenience of explanation, the schematic diagrams will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which shall not limit the protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production.
[0034...
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A temperature detection structure comprises a semiconductor substrate in which a TSV interconnection structure is formed, a power circuit which is used for applying a test current to the TSV interconnection structure, a capacitance test circuit which is used for measuring the value of depletion capacitance between the TSV interconnection structure and the semiconductor substrate when the power circuit is applying a test current to the TSV interconnection structure, and a calculation module which is used for calculating the temperature of the semiconductor substrate based on the obtained value of depletion capacitance. According to the temperature detection structure, the temperature of the semiconductor substrate is detected in real time, which is conductive to thermal management of a die or package structure.
Description
technical field [0001] The invention relates to testing technology, in particular to a temperature detection structure. Background technique [0002] With the continuous development of semiconductor technology, the feature size of semiconductor devices has become very small. It is becoming more and more difficult to increase the number of semiconductor devices in a two-dimensional packaging structure. Therefore, three-dimensional packaging has become a method that can effectively improve chip integration. degree method. Current three-dimensional packaging includes die stacking based on gold wire bonding, package stacking and three-dimensional stacking based on through silicon vias (Through Silicon Via, TSV). Among them, the three-dimensional (3D) stacking technology using through-silicon vias has the following three advantages: (1) high-density integration; Problems such as signal delay in chip (SOC) technology; (3) Using TSV technology, chips with different functions (suc...
Claims
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IPC IPC(8): G01K7/34
Inventor 甘正浩
Owner SEMICON MFG INT (SHANGHAI) CORP