Processor chip emulator with non-volatile memory

Abstract

The invention discloses an implementation method of a processor chip simulator with a nonvolatile memory. When an equivalent control logic module is under a user mode, the read-write operation time sequence, the control function and the performance of the nonvolatile memory are simulated and made equivalent and are cooperated with a SRAM (Static Random Access Memory) to enable the read-write operation time sequence, the function and the performance of the nonvolatile memory in a product chip to be equivalent; when a user program stops to be operated and a user downloads a code and fills or revises data to the area of the nonvolatile memory through integrated development environment software, a monitoring module controls the equivalent control logic module to be under a monitoring mode, the equivalent control logic module and the SRAM memory are jointly made equivalent to the operation time sequence, the function and the performance of the standard nonvolatile memory, and the area of the nonvolatile memory is directly accessed and operated by an operation standard SRAM memory instruction issued by the integrated development environment software. By use of the implementation method, the usability and the debugging performance of the simulator are improved while the function and performance authenticity of the simulator can be guaranteed.

Description

technical field [0001] The invention relates to the field of emulators, in particular to a processor chip emulator with nonvolatile memory. Background technique [0002] There is a user program developed by the user in the processor chip. In the writing and debugging of the user program, the tool used is generally an emulator. The emulator uses an emulation chip containing various functions of the product processor chip to simulate the working behavior of the product processor chip, and the emulation chip and other parts of the emulator (program memory for storing user programs, data memory for storing data, and user The integrated development environment on the computer, etc.) cooperates to realize the simulation operation of the user program and various debugging functions. [0003] Many processor chips have non-volatile memory, such as EEPROM (Electrically Erasable Programmable Read-Only Memory, Electrically Erasable Programmable Read-Only Memory), etc., which can be use...

AI Technical Summary

Problems solved by technology

When the user downloads codes to the memory in the emulator through the interface of the integrated development environment, fills and rewrites data in the memory of the emulator through the memory window of the integrated development environment, the target address and data are directly issued in the way of operating the SRAM, and will not Considering that if the target memory is a non-volatile memory, it needs to operate in accordance with the corresponding operation mode and timing, so the existing emulator usually has two implementation methods, the first is to directly make the non-volatile memory into a pure non-volatile memory in the emulator SRAM features to ensure that the standard integrated development environment can be directly operated, but it will cause the non-volatile memory in the emulator to be inconsistent with the product chip in terms of function and performance; the second is to replace the non-volatile memory with SRAM plus equivalent control logic The way of volatile memory ensures the consistency of functional performance, but you need to ask the integrated development environment manufacturer or add memory operation patches on the integrated development environment by yourself, and customize the memory location, size, and characteristics of your own chip.

However, when the emulator debugs the user program, it only pays attention to the consistency of the memory function and performance with the product chip when the user program is executed at full speed. The functional performance is consistent with the product chip, but more concerned about the download speed, filling response speed and other performance. The second method adds a patch layer, which needs to be downloaded, filled and modified, which will reduce the debugging performance. At the same time, it is very troublesome to make a patch layer according to different non-volatile memory characteristics of different chips

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