Semiconductor structure and formation method thereof

Abstract

The invention discloses a semiconductor structure and a formation method thereof. The method comprises steps that a substrate having a dummy grid is provided, a deuterium-doped source-drain epitaxial layer is formed at two sides of the dummy grid on the substrate through the gas phase epitaxial deposition process; the dummy grid is removed, a grid structure with a gate oxide is formed at the position of the dummy grid, and deuterium enters the gate oxide. Through the acquired semiconductor structure, as deuterium is made to enter the gate oxide, a stable covalent bond is formed at an interface of the gate oxide, a dangling bond existence problem can be effectively improved, moreover, recovery capability of the device for responding to hot carrier's effects can be improved, and thereby influence of the hot carrier's effects on device performance is reduced.

Description

Technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a method of forming the same. Background technique [0002] At present, semiconductor manufacturing technology has been rapidly developed. Such as Figure 1-6 A common MOS formation process in the prior art is shown. include: [0003] Such as figure 1 As shown, a gate structure 2 is formed on the substrate 1; [0004] Such as Figure 2-Figure 4 As described, a protective layer 3 is deposited on the substrate 1 to cover the gate structure 2; reactive ion etching is performed to remove part of the protective layer 3, and the protective layer 3 is inclined at both sides of the gate structure 2; further Remove the part of the protective layer 3 on the substrate 1 to form a gate sidewall 4; [0005] Such as Figure 5 As shown, the source and drain electrodes 5 are epitaxially formed on both sides of the gate 2 on the substrate 1, and doped in-situ; [0...

AI Technical Summary

Problems solved by technology

[0007] However, including but not limited to the semiconductor structure formed through the above steps, dangling bonds will be formed inside. These dangling bonds mainly occur on the surface or interlayer interface, which will cause holes, dislocations, and the introduction of other impurities. situation

[0008] In addition, in the current MOS manufacturing process, another issue that arises is the impact of hot carrier effects on device performance

Special attention is paid to the fact that in smaller-sized devices, when they are used at higher voltages, the carriers in the channel will enter the insulating layer because they have enough energy, thus affecting the performance of the device

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