Digital chip ADC output data receiving method and digital chip

Abstract

The invention provides a digital chip ADC output data receiving method and a digital chip. When LVDS channel associated clock generation data sampling receiving clocks outputted by an ADC are used, the sampling clocks are divided into multiple phases. The optimal phase of the sampling receiving clocks Iclk capable of receiving the ADC data under the current environment is searched in case of chip enabling or user requirements, and the phase coefficient of the optimal phase is configured to a phase-locked loop so as to generate the sampling receiving clocks Iclk having the optimal phase; and then the sampling receiving clocks Iclk having the optimal phase are utilized to receive the output data of the ADC. According to the method, the internal phase-locked ring part of the digital chip is optimized, the phase-locked ring output clock phase dynamic reconfiguration function is supported, and the self-test process of the digital chip ADC interface is also additionally arranged so that the optimal phase of the sampling receiving clocks Iclk can be calculated, and the receiving sampling clock edge is ensured to be close to the middle of a data sampling window as much as possible.

Description

technical field [0001] The application belongs to the field of data transmission, and in particular relates to a method for a digital chip to receive ADC output data and the digital chip. Background technique [0002] The high-speed development of computer technology, communication technology and microelectronic technology has greatly promoted the development of ADC technology, and the sampling rate of ADC as a key technical index has also become higher and higher. In modern electronic design, digital chips (FPGA / CPLD / ASIC) need to receive and process high-speed output data from ADC. At present, the data output interface of mainstream ADCs on the market is still a low-voltage differential signal LVDS (Low-Voltage Differential Signaling) interface. Therefore, when designing an ADC interface, whether it can reliably receive high-speed LVDS data from the ADC becomes very important. [0003] Existing technology solutions such as figure 1 As shown, the digital chip receives the...

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Problems solved by technology

[0005] This application provides a method for a digital chip to receive output data from an ADC to solve the problem of bit errors in the received data due to product process and environmental changes when the digital chip receives output data from the ADC in the prior art. The problem of low reliability, while providing a digital chip that receives ADC output data

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