Uniform stainer array multi-warp instruction fetching circuit and method

Abstract

The invention belongs to the technical field of integrated circuits, and relates to a uniform stainer array multi-warp instruction fetching circuit and method. The circuit comprises a warp scheduling unit (1), instruction fetching information fifo (2), an external icache (3) and at least two warp pc address calculation units (4), wherein each pc address calculation unit corresponds to one warp. The multi-warp instruction fetching process can be realized, and latency of a memory is effectively hidden to improve the throughput capacity of a uniform stainer array.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and relates to a unified dyer array multi-warp indexing circuit and a method. Background technique [0002] The unified colorer array completes the unified coloring function of vertices and pixels. In the unified shader array, the instruction has a memory access instruction, and the subsequent instruction needs the result returned by the memory access instruction to access the memory. Because the memory access takes a long time to return, the operation unit has to stop and wait. After the memory returns the result, the following instructions can continue to run. [0003] Therefore, in this case, the arithmetic unit is idle for a long time. In order to make full use of the idle time of the computing unit, a multi-warp switching method is adopted to insert multiple instructions of other warps between such instructions of the warp to hide its memory access delay, so as to make full use...

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Problems solved by technology

[0003] Therefore, in this case, the computing unit is idle for a long time

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