Partial scanning-based integrated circuit fault injection attack simulation method

Abstract

The present invention discloses a partial scanning-based integrated circuit fault injection attack simulation method. The method includes the following steps of: extracting a target register for fault injection; inserting partial scanning; generating a fault vector; performing fault injection and simulation; and performing security evaluation. According to the partial scanning-based integrated circuit fault injection attack simulation method of the invention, scanning chains are inserted into some registers which are selected from an original net list obtained after circuit integration, integrated circuit fault injection attack simulation is realized, resource consumption is reduced, and automation can be realized.

Description

technical field [0001] The invention belongs to the field of integrated circuit security, and in particular relates to a partial scan-based integrated circuit fault injection attack simulation method. Background technique [0002] Integrated circuit fault injection attack simulation is a technology that simulates the effect of fault injection attack to detect and evaluate the anti-fault injection attack ability of circuit design. Existing IC fault injection attack simulation methods mainly include chip testing [1], software simulation [2] and hardware simulation [3]-[4]. Chip testing performs a real fault injection attack on the manufactured chip, which has low detection efficiency, high cost, long design modification cycle, and extremely high cost. Software simulations run slower and take longer to obtain simulation results. Hardware simulation utilizes FPGA prototyping platforms to accelerate the simulation process. Existing FPGA-based hardware simulation methods mainly...

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Problems solved by technology

The former brings huge resource consumption, while the latter uses full scan technology to bring high resource consumption

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