Control method of ultra-thin wafer warpage
A control method and wafer technology, applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of ultra-thin wafer bending, waste of edge materials, inability to wafer, etc., to reduce the degree of warpage , the effect of reducing surface tension and improving consistency
Active Publication Date: 2019-12-06
任彩丽
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Problems solved by technology
[0004] (1) The edge material is wasted, which increases the cost;
[0005] (2) At the center and edge of the wafer, the surface stress is different, resulting in differences in chip performance;
[0006] (3) The warped wafer does not match the subsequent process, and the subsequent process cannot or needs to treat this wafer specially
The surface tension of a single chip 2 is the same, if the surface tension of each single chip 2 is arranged in the same way, it will cause an additive effect, causing the ultra-thin wafer to bend in a certain direction
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[0037] Preferred embodiments of the present invention will be described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described here are only used to illustrate and explain the present invention, not to limit the present invention.
[0038] A method for controlling the warpage of an ultra-thin wafer, the ultra-thin wafer includes several single chips, and each single chip includes several cells.
[0039] Such as figure 2 As shown, in the layout design, the direction of the surface tension of a single chip is determined according to the geometry of the layout design of the single chip, and then the single chip is arranged so that the surface tension of any adjacent single chip points in the opposite direction.
[0040] Such as image 3 As shown, when the single chip is designed, the length of each cell contained in the single chip is designed to be twice the width;
[0041] Each cell group 4 is made up of the fir...
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The invention discloses an ultrathin wafer warping control method. In layout design, direction of surface tension of each single chip is judged according to the geometrical shape thereof in the layout design; and then, the chips are arranged in a manner that directions of surface tensions of any two adjacent chips are opposite. The method enables the surface tensions at all places to be consistent in the initial layout design phase of an ultrathin wafer, thereby reducing warping and improving chip performance consistency; the method does not cause waste of edge materials nor need to add extra technical processing programs; and the method is suitable for control of warping in the ultrathin wafer production process.
Description
technical field [0001] The invention relates to the technical field of ultra-thin chip manufacturing technology, which is used for controlling the warping degree of the ultra-thin wafer during the manufacturing process, in particular to a method for controlling the warping of the ultra-thin wafer. Background technique [0002] In order to improve product performance, ultra-thin chip design is being used more and more widely. Usually, the thickness of IC wafer is about 1 mm. If it is thinned to less than 100 microns, the wafer will bend and deform, especially on large diameter wafers (8 inches, 12 inches...). [0003] In order to reduce the degree of warping of ultra-thin wafers, many studies have been carried out. The U.S. patent with the publication number US 2013 / 0001766 introduces a process treatment method, the Taiko process, which achieves the purpose of controlling the bending degree of the intermediate wafer material by leaving a circle of normal thickness wafer mate...
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IPC IPC(8): H01L21/67H01L27/02
CPCH01L21/67288H01L27/0207Y02P80/30
Inventor 步建康徐朝军李士垚
Owner 任彩丽