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Packaging technology of chip and packaging structure

A packaging process and chip technology, applied in the direction of semiconductor/solid-state device components, semiconductor devices, electrical components, etc., can solve the problem that the chip cannot be targeted and effectively protected.

Inactive Publication Date: 2017-05-31
NAT CENT FOR ADVANCED PACKAGING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Chip packaging is an extremely important part of the semiconductor industry. The existing packaging structure cannot provide targeted and effective protection for chips.

Method used

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  • Packaging technology of chip and packaging structure
  • Packaging technology of chip and packaging structure
  • Packaging technology of chip and packaging structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0043] Figure 1A It is a schematic diagram of a chip packaging process flow provided in the first embodiment of the present invention, Figure 1B-1H It is a schematic structural cross-sectional view of each step in a chip packaging process provided in the first embodiment of the present invention. reference Figure 1A-1H The packaging process provided in this embodiment specifically includes the following steps:

[0044] Step 110: Provide a substrate, and form a cavity in the substrate.

[0045] reference Figure 1B , The substrate 11 with the cavity 111 can be manufactured through processes such as etching, electroplating, injection molding, and die casting. If the power of the chip is large, a metal substrate can be used to package the chip; if the chip is a high-frequency chip, a ceramic substrate can be used to package the chip. In the actual design, a suitable substrate material will be selected according to the characteristics of the chip.

[0046] Step 120: Place at least on...

Embodiment 2

[0070] figure 2 It is a schematic cross-sectional view of a chip package structure provided in the second embodiment of the present invention, refer to figure 2 , A chip packaging structure provided in an embodiment of the present invention specifically includes: a substrate 21, at least one first chip 22, a protective layer 23, a plurality of first wires 24, a first insulating layer 25, a connecting pillar 26, The second chip 27, the second insulating layer 28, the plurality of second wires 29, the third insulating layer 30 and the plurality of solder balls 31.

[0071] reference figure 2 , Specifically, a cavity is formed in the substrate 21;

[0072] At least one first chip 22 is arranged on the bottom surface of the cavity, the electrode of the first chip 22 is formed with first protrusions 121, and the upper surface of the substrate is lower than that of the first protrusion 121 Upper surface

[0073] The protective layer 23 is formed on each of the first chips 22 and the su...

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PUM

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Abstract

The invention provides a packaging technology of a chip and a packaging structure. The packaging technology comprises steps of forming a cavity in a substrate, setting first chips at least one of which is equipped with a first boss on the bottom face of the cavity, and allowing the bottom face of the substrate to be lower than the surface of the first boss; forming protection layers on the first chips and the substrate, and forming first wires electrically connected with the first bosses on the protection layers; forming first insulation layers and connection columns electrically connected with the first wires on the first wires; setting at least one second chip on the first insulation layers and forming second insulation layers on the second chips and the first insulation layers; and forming a window in a second insulation layer and setting welding balls electrically connected with the second wires. According to the invention, the cavity and the protection layers are used for protecting the chips; electrodes of the chips are led out to the welding balls by use of the wires and the welding balls; and data transmission is performed through the welding balls and the chips.

Description

Technical field [0001] The embodiment of the present invention relates to the field of chip packaging, in particular to a chip packaging process and packaging structure. Background technique [0002] Chip packaging means that the produced integrated circuit die is placed on a substrate that plays a supporting role, the electrodes are led out, and then fixed and packaged as a whole. In the chip packaging process, the die is generally placed on the packaging substrate and aligned with the placement site so that the solder balls are aligned with the pre-solder on the substrate. The substrate is usually composed of an organic material or a laminate material, which is subsequently heated and reflowed to form an electrical connection between the chip and the package substrate. Chip packaging is an extremely important part of the semiconductor industry. The existing packaging structure cannot effectively protect the chip. Summary of the invention [0003] The invention provides a chip ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/98H01L25/065H01L23/31H01L21/60
CPCH01L24/80H01L25/0657H01L25/50H01L23/3128H01L2224/73267H01L2224/32225H01L2224/12105H01L2224/04105H01L2224/92244H01L2924/15153
Inventor 林挺宇陈峰
Owner NAT CENT FOR ADVANCED PACKAGING