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A chip package and method thereof, chip, video recording device and electronic device

A technology of chip packaging and electronic equipment, applied in the direction of circuits, electrical components, semiconductor devices, etc., can solve problems such as easy crossover, and achieve the effect of avoiding crossover

Active Publication Date: 2018-09-21
APPOTECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] An object of the embodiments of the present invention is to provide a chip package and its method, chip, video recording equipment and electronic equipment, which solves the technical problem that the existing logic chip and memory chip are prone to cross when wiring

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  • A chip package and method thereof, chip, video recording device and electronic device
  • A chip package and method thereof, chip, video recording device and electronic device
  • A chip package and method thereof, chip, video recording device and electronic device

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Embodiment Construction

[0031] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0032] figure 1 A schematic structural diagram of a chip package is provided for an embodiment of the present invention. Such as figure 1 As shown, the chip package 100 is based on the MCP (Multi-chippackage, multi-chip package) design, the memory chip 11 and the logic chip 12 are packaged, and the chip package 100 can also be provided without significantly increasing the size of each chip. integration and storage capacity.

[0033] In some embodiments, the memory chip 11 may include an SDR SDRAM chip or a DDR SDRAM chip (Synchronous Dynamic Random Access Memory, Synchronous Dynamic Random Acces...

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Abstract

The invention relates to the technical field of chip packaging, in particular to a chip package body and its method, a chip, video recording equipment and electronic equipment. Wherein, the chip package includes a memory chip and a logic chip, the logic chip includes a first row of pin groups and a second row of pin groups, and the first row of pin groups and the second row of pin groups include at least each The pins correspond to the connected pins one by one, and at least one redundant data pin is provided at one end of the first row of pin groups. When packaging a logic chip and a memory chip, when the specific pins (for example, power pins) between the logic chip and the memory chip are not facing each other, or they are located on the same side but in order to realize the mutual connection between the corresponding specific pins If there is a wire crossover, the redundant data pin can be used to connect with other data pins of the memory chip, so as to avoid the crossover of the wire bonding of the data pins in order to realize the interconnection between specific pins problem occurs.

Description

technical field [0001] The invention relates to the technical field of chip packaging, in particular to a chip package body and its method, a chip, video recording equipment and electronic equipment. Background technique [0002] At present, many memory chips are usually packaged together with the logic chip in a packaging method. For example, the DDR memory chip and the logic chip are placed on the carrier substrate separately, and then the output / input pins of the DDR chip and the logic chip are connected separately by wire bonding. The output / input pins of the chip are connected to the pads of the carrier substrate, so that the DDR memory chip and the logic chip are packaged into a package structure. [0003] However, in the process of realizing the present invention, the inventor found that the prior related art has at least the following problems: since the voltage pins or ground pins of the logic chip and the voltage pins or ground pins of the DDR memory chip are not l...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/56H01L23/31H01L23/48
CPCH01L21/56H01L23/31H01L23/48H01L2224/05554H01L2224/48145H01L2924/00012
Inventor 朱国钟梁明亮莫昌文许夏辉
Owner APPOTECH