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Method for preparing high performance semiconductor field effect transistor device

A field-effect transistor and semiconductor technology, which is applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of large off-current of MOSFET devices, increased power consumption of integrated circuit products, and steep doping concentration gradients, etc. , to achieve the effects of reducing the off-current, suppressing diffusion, and solving the problem of low doping concentration

Active Publication Date: 2017-08-11
ZHEJIANG UNIV
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Problems solved by technology

Due to the diffusion of dopant ions in the semiconductor, it is difficult to form a semiconductor p-n junction with high doping concentration and steep doping concentration gradient, resulting in a large turn-off current of MOSFET devices
These defects will cause problems such as increased power consumption of integrated circuit products when the scale of integrated circuits is getting larger and larger today.

Method used

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  • Method for preparing high performance semiconductor field effect transistor device
  • Method for preparing high performance semiconductor field effect transistor device
  • Method for preparing high performance semiconductor field effect transistor device

Examples

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Embodiment 1

[0048] Embodiment 1: In this embodiment, the semiconductor substrate is a germanium substrate 10, and the preparation method comprises the following steps:

[0049] (1) if figure 1 As shown in (a), a first insulating layer 11 is deposited on the germanium substrate 10, the material of the first insulating layer 11 can be silicon oxide or silicon nitride, and the thickness is about several hundred nanometers;

[0050] (2) if figure 1 As shown in (b), a hole is etched on the first insulating layer 11 until the germanium substrate 10 by means of photolithography and etching, and the position of the hole is the source and drain region of the Ge MOSFET device;

[0051] (3) if figure 2 As shown in (a), a groove structure is formed on the germanium substrate 10 . The first step is to use the first insulating layer 11 as a mask, and use reactive plasma etching or solution etching to form grooves on the germanium substrate 10. The depth of the grooves is several nanometers to tens of...

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Abstract

The invention discloses a method for preparing a high performance semiconductor field effect transistor device. The method comprises steps of first defining a source region and a drain region on a semiconductor substrate, etching the source and drain regions, and forming grooves; depositing semiconductor material in etched grooves to form a source and a drain by atmospheric or low temperature physical vapor deposition; recrystallizing the semiconductor deposited in the source and drain regions by laser annealing to form source and drain p-n junctions; and finally depositing a gate insulating layer and a metal gate to form a semiconductor field effect transistor device. The method deposits the semiconductor material as the source and the drain in the grooves etched in the semiconductor substrate by the atmospheric or low temperature physical vapor deposition technology, increases the doping concentration of the source and drain p-n junctions in the MOSFET device, and reduces the doped ion diffusion in the semiconductor deposition process of the source and drain regions. The method of the invention combines the feature that the laser pulse time is short in the laser annealing technology to suppress the diffusion of doped ions during the annealing process.

Description

technical field [0001] The invention belongs to the field of semiconductor materials, and relates to a method for preparing a high-performance semiconductor field effect transistor device. Background technique [0002] Silicon trench field effect transistor (Si MOSFET) is the most basic unit of modern integrated circuits, and is the basis for integrated circuits to realize functions such as computing and storage. The most important index to measure the performance of a MOSFET device is the turn-on current of the device, and the performance of the device can be improved by reducing the channel length of the MOSFET device. After half a century of technological progress, the feature size of MOSFET devices has become smaller and smaller. At present, the channel length of mass-produced MOSFET devices has reached 20nm. The method of further reducing the size of the device will lead to serious short-channel effects, and it is difficult to further improve the performance of integra...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L29/78
CPCH01L29/66636H01L29/66795H01L29/78H01L29/785
Inventor 张睿赵毅
Owner ZHEJIANG UNIV
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