GaN chip and manufacturing method thereof
A chip and buffer layer technology, applied in the field of microelectronics, can solve the problems of reducing the working reliability of the device, the working life of the chip, not as stable and mature as the CMOS process, and the breakdown of the buffer layer device, so as to improve the user experience and improve the gate leakage current. , The effect of improving the working life
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[0045] The technical solution of the present invention will be further described in detail below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following description.
[0046] Such as figure 1 , shown in 2, a GaN chip, including a substrate, a source, a drain and a gate, including:
[0047] (1) Silicon substrate 701;
[0048] (2) SiN or AlN nucleation layer 501, the SiN or AlN nucleation layer 501 is disposed on the silicon substrate 101;
[0049] (3) a doped GaN buffer layer 401, the doped GaN buffer layer 401 is disposed on the SiN or AlN nucleation layer 501;
[0050] (4) AlN or GaN isolation layer 301, the AlN isolation layer or GaN isolation layer 301 is disposed on the doped GaN buffer layer 401;
[0051] (5) GaN / InGaN / AlN / GaN double heterojunction, the GaN / InGaN / AlN / GaN double heterojunction is arranged on the AlN or GaN isolation layer 301;
[0052] The GaN / InGaN / AlN / GaN double heterojunction i...
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