Semiconductor device and manufacturing method thereof
A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., can solve problems such as multiple costs
Active Publication Date: 2019-11-22
VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
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Problems solved by technology
However, the above-mentioned known methods all require excessive cost
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[0047] The semiconductor device and its manufacturing method of the present invention will be described in detail below. It should be appreciated that the following description provides many different embodiments or examples for implementing different aspects of the invention. The specific elements and arrangements described below are only for the purpose of simply and clearly describing the present invention. Of course, these are only examples rather than limitations of the present invention. Furthermore, repeated reference numerals or designations may be used in different embodiments. These repetitions are only for the purpose of simply and clearly describing the present invention, and do not represent any relationship between the different embodiments and / or structures discussed. Furthermore, when it is mentioned that a first material layer is located on or above a second material layer, it includes the situation that the first material layer is in direct contact with the...
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The p invention provides a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a substrate, an epitaxial layer, a first-conductivity-type first well arranged in the substrate and the epitaxial layer, a second-conductive-type first burying layer and a second-conductive-type second burying layer, a first-conductivity-type second well, a second-conductive-type third burying layer, a second-conductive-type doping region, a gate structure, a drain contact plug, and a source contact plug. The second-conductive-type first burying layer and the second-conductive-type second burying layer are arranged at the two sides of the first-conductivity-type first well; the first-conductivity-type second well is arranged in the epitaxial layer and is in contact with the first-conductivity-type first well directly; the second-conductive-type third burying layer is arranged in the first-conductivity-type first well and / or first-conductivity-type second well; and the second-conductive-type doping region is arranged in the first-conductivity-type second well. The breakdown voltage of the semiconductor device can be increased at a low cost, so that the semiconductor device can be used in applications with the high operation voltage.
Description
technical field [0001] The present invention relates to semiconductor technology, and more particularly to semiconductor devices and methods of manufacturing the same. Background technique [0002] Due to the increasing demand for high-yield devices, two or more semiconductor devices are integrated into a single chip. Bipolar transistor-complementary metal oxide semiconductor-double diffused metal oxide semiconductor transistor (Bipolar-CMOS-DMOS, BCD) has been widely used in device integration. Bipolar transistor-complementary metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor transistor technology is a bipolar transistor, complementary metal-oxide-semiconductor (complementary metal-oxide-semiconductor, CMOS) and double-diffused metal-oxide semiconductor transistor (double diffused metal-oxide-semiconductor transistor, DMOS) technology is integrated in a single chip. [0003] At present, the process of bipolar transistor-complementary metal oxide semicond...
Claims
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IPC IPC(8): H01L27/06H01L21/8249H01L29/06
CPCH01L21/8249H01L27/0623H01L29/0623
Inventor 陈巨峰周苇俊邱建维
Owner VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION