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Measurement method of epitaxial wafer resistivity based on super back-sealed substrate

A measurement method and epitaxial wafer technology, which are used in semiconductor/solid-state device testing/measurement, circuits, electrical components, etc., can solve problems such as inaccurate measurement results, and achieve accurate measurement results.

Active Publication Date: 2020-01-07
HEBEI POSHING ELECTRONICS TECH
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Problems solved by technology

[0004] In view of this, an embodiment of the present invention provides a method for measuring the resistivity of an epitaxial wafer based on a super back-sealing substrate to solve the problem of using the HG-CV method to measure the resistivity of an epitaxial wafer of a super back-sealing substrate in the prior art. Technical issues with inaccurate measurements

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  • Measurement method of epitaxial wafer resistivity based on super back-sealed substrate
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  • Measurement method of epitaxial wafer resistivity based on super back-sealed substrate

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Embodiment Construction

[0029] In order to make the object, technical solution and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0030] Please refer to figure 1 , figure 1 It is an implementation flowchart of a method for measuring the resistivity of an epitaxial wafer based on a super back-sealing substrate provided by an embodiment of the present invention, including the following steps:

[0031] In step S101, the polycrystalline back-sealing layer of the epitaxial wafer based on the super back-sealing substrate is processed to expose the silicon dioxide back-sealing layer, and the position of the treatment includes the measurement position.

[0032] In the embodiment of the present invention, the po...

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Abstract

The invention discloses an epitaxial wafer resistivity measuring method based on a super sealing substrate, and relates to the semiconductor technology field. The epitaxial wafer resistivity measuring method comprises steps that the polycrystal sealing layer of the epitaxial wafer based on the super sealing substrate is processed, and a silicon dioxide sealing layer is exposed, and a processed position comprises a measuring position; the first cleaning of the processed epitaxial wafer is carried out in pure water; the epitaxial wafer after the first cleaning is rinsed in hydrofluoric acid solution; the second cleaning of the rinsed epitaxial wafer is carried out in the pure water; the epitaxial wafer after the second cleaning is boiled in a hydrogen peroxide solution at a preset temperature for a preset time; the third cleaning of the epitaxial wafer in the pure water is carried out; the epitaxial wafer is dried by being blown by nitrogen; and finally, a mercury probe capacitance-voltage method measuring device is used to measure the epitaxial wafer. Measuring results are accurate.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for measuring the resistivity of an epitaxial wafer based on a super back-sealing substrate. Background technique [0002] In the silicon epitaxy process, a back seal layer needs to be covered on the back of the substrate. Usually, a layer of silicon dioxide (LTO) is covered on the back of the substrate as a back-sealing layer. The Super Sealing (Super Sealing) substrate is a new type of polysilicon (POLY) that is covered with a layer of polysilicon (POLY) on the surface of the LTO back-sealing layer. The substrate of the double-layer back seal structure. [0003] When measuring silicon epitaxial resistivity, the mercury probe capacitance voltage method (HG-CV) is usually used to measure the resistivity of silicon epitaxial wafers through the Back-Surface-Return-Contact structure. This method requires the substrate of the epitaxial wafer to be in close contact w...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66H01L21/304H01L21/02
CPCH01L21/02057H01L21/3043H01L22/14
Inventor 张佳磊薛宏伟张志勤王铁刚
Owner HEBEI POSHING ELECTRONICS TECH