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Semiconductor device

A semiconductor and device technology, applied in the field of semiconductor integrated circuits, can solve the problems of reducing the layout area, limited safe working area and electrostatic capacity, unable to meet the needs of product functional applications, etc., to suppress conduction, expand the safe working area and The effect of electrostatic protection ability

Active Publication Date: 2017-12-29
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] Depend on Figure 1A and Figure 1B It can be seen that the source structure of two adjacent cell structures is shared, which can reduce the layout area and maximize the performance area ratio; however, for some high-voltage devices, this structure will have a safe operating area and Electrostatic Capability Limited
Can't even meet the needs of product functional applications

Method used

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  • Semiconductor device
  • Semiconductor device
  • Semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0051] The semiconductor device of the first embodiment of the present invention:

[0052] Such as Figure 2A Shown is a plan view of the semiconductor device 1 according to the first embodiment of the present invention; Figure 2B is along Figure 2A The cross-sectional view of the BB line; the semiconductor device 1 of the first embodiment of the present invention is one of LDMOS, DDDMOS and DEMOS, and the unit structures of a plurality of semiconductor devices 1 are integrated on the same semiconductor substrate, and each of the unit structures includes: Source structure, drain structure, planar gate structure.

[0053] The planar gate structure includes a gate dielectric layer such as a gate oxide layer and a polysilicon gate 2 sequentially formed on the surface of the high-voltage P well 7; the high-voltage P well 7 serves as a body region 7 and is covered by the polysilicon gate 2 The 7 surface is used to form a channel connecting the source and drain.

[0054] The s...

no. 3 example

[0073] The semiconductor device of the third embodiment of the present invention:

[0074] Such as Figure 4A Shown is a plan view of the semiconductor device of the third embodiment of the present invention; Figure 4B is along Figure 4A The cross-sectional view of the EE line; the difference between the semiconductor device 1b of the third embodiment of the present invention and the semiconductor device 1 of the first embodiment of the present invention is that in the device of the third embodiment of the present invention, the first contact hole 6a is in the top view The first contact hole 6 a spans the entire body lead-out region 4 and the interface between the body lead-out region 4 and the source regions 3 on both sides.

no. 4 example

[0075] The semiconductor device of the fourth embodiment of the present invention:

[0076] Such as Figure 5A Shown is a plan view of a semiconductor device 1c according to a fourth embodiment of the present invention; Figure 5B is along Figure 5A The cross-sectional view of the FF line; Figure 5C is along Figure 5A The cross-sectional view of the GG line; the difference between the semiconductor device 1c of the fourth embodiment of the present invention and the semiconductor device 1a of the second embodiment of the present invention is that the source region 3 and the body lead-out region 4 pass across the The source region 3 and the first contact hole 6a4 of said body lead-out region 4 are connected to the source electrode consisting of the front metal layer. The first contact hole 6a4 is in the shape of a strip in plan view.

[0077] A second contact hole 6a5 located only in the body lead-out region 4 is also formed in the body lead-out region 4, and the top of ...

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PUM

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Abstract

The invention discloses a semiconductor device, and the device is one of LDMOS, DDDMOS and DEMOS. Each unit structure comprises a source end structure, a drain end structure, and a plane gate structure. All unit structures are arranged in a multi-finger-shaped array structure in a top view plane, and two adjacent unit structures shared one source end structure. A source region is of a continuous structure in a width direction of a trench and is provided with a first contact hole which is across the source region and a volume leading-out region; or, the source region is of a structure where the volume leading-out region structure is inserted in the width direction of the trench, and the first contact hole may be inserted into the volume leading-out region of the source region, and can improve the control of the electric potential of a volume region at the peripheral side of the source region and improve the collection of positive charges formed during the biasing reversal breakdown of a PN junction of the drain end of a device through the volume leading-out region, thereby facilitating the inhibition of the conduction of a parasitic triode, enlarging the safety work area of the device and improving the electrostatic protection capability of the device.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a semiconductor device. Background technique [0002] Compared with ordinary MOS devices, high-voltage semiconductor devices usually use lateral diffusion MOS devices (LateralDiffusion MOSFET, LDMOS), double diffusion drain MOS devices (Double Diffusion Drain MOSFET, DDDMOS) and extended drain MOS devices (Drain Extended MOSFET, DEMOS), etc. , when the layout design is arranged in an array, the adjacent drains, sources and bodies are connected in pairs to reduce the layout area and maximize the performance-to-area ratio. [0003] Such as Figure 1A Shown is a plan view of an existing high-voltage semiconductor device; Figure 1B is along Figure 1A A cross-sectional view of the AA line; the high-voltage semiconductor device 101 includes a plurality of unit structures integrated together, Figure 1A 2 unit structures are shown in ; each unit structure includes: [0004] A pl...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02H01L27/088
CPCH01L27/0207H01L27/0292H01L27/088
Inventor 苏庆
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP