Nanowire memory structure and preparation method thereof

Abstract

The invention provides a nanowire memory structure and a preparation method thereof. The nanowire memory structure comprises the components of a semiconductor substrate with a heavily doped epitaxiallayer on the surface; a first isolating dielectric layer, a ground selecting gate electrode layer, a bit line gate electrode layer, a string selecting gate electrode layer, and multiple second isolating dielectric layers among the ground selecting gate electrode layer, the bit line gate electrode layer and the string selecting gate electrode layer, wherein the first isolating dielectric layer, theground selecting gate electrode layer, the bit line gate electrode layer, the string selecting gate electrode layer and the multiple second isolating dielectric layers are arranged on the semiconductor substrate; a semiconductor channel which penetrates through the ground selecting gate electrode layer, the bit line gate electrode layer and the string selecting gate electrode layer; and a gate electrode dielectric layer which packages the sidewall of the semiconductor channel, wherein the semiconductor channel is an III-V family single-crystal semiconductor nanowire which vertically and upwards grows epitaxially on the heavily doped epitaxial layer. According to the memory structure, the III-V family single-crystal semiconductor nanowire which vertically and upwards grows epitaxially on the heavily doped epitaxial layer is used as the vertical channel; and compared with an existing vertical channel type NAND structure, the nanowire memory structure has advantages of further simplifieddevice structure, easy controlling for the preparation process, and high yield rate of products.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a nanowire memory structure and a preparation method thereof. Background technique [0002] For NAND memories with different architectures, they can be divided into three-dimensional floating gate memories and three-dimensional charge trap memories according to the material of the storage layer. For the former three-dimensional floating gate memory, because the polysilicon floating gate is used as the storage layer, the area of ​​the storage unit is larger, and it is more difficult to realize the stacking of more layers of storage units. Therefore, the area is mainly realized by placing the peripheral circuit under the storage array. reduction. For the latter three-dimensional charge trap memory, it can be divided into vertical gate type and vertical channel type. The three-dimensional charge-trapping flash memory structure based on the vertical gate structure is mo...

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Problems solved by technology

[0005] However, in the existing vertical channel type three-dimensional charge trapping memory, the device channel material adopts polysilicon film, which requires good crystallinity and large crystal grains, and at the same time requires the thickness of the polysilicon film channel to be as thin as possible. Difficult to balance, affecting product yield

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