Semiconductor memory device and reading method thereof

Abstract

The invention provides a semiconductor storage device and a readout method thereof. The flash memory of the present invention includes: a memory cell array; a page buffer / readout circuit, which keeps the data of a selected page of the memory cell array; a decoding / selection circuit, based on a column address, from the data held by the page buffer select n-bit data; and an n-bit data bus connected to the decoding / selection circuit. The decoding / selection circuit further connects n / 2-bit even-numbered address data to the lower bit of the data bus and n / 2-bit odd-numbered address data to the upper bit of the data bus based on the column address, and then, at the beginning When the address is an odd address, data at an odd address and data at an even address next to the odd address are selected.

Description

technical field [0001] The invention relates to a semiconductor storage device and a readout method thereof, in particular to a readout method of a NAND flash memory. Background technique [0002] In the NAND flash memory, data is read and programmed in page units, and the page data is stored in a page buffer. The flash memory disclosed in Japanese Patent Application Laid-Open No. 2012-253591 includes a first mode in which data stored in a page buffer is transferred with a first bit width and a second mode in which data stored in a page buffer is transferred with a second bit width. Corresponds to multiple action modes. [0003] [Problem to be Solved by the Invention] [0004] Some NAND-type flash memories are equipped with a serial interface for serially inputting / outputting data with a small number of terminals. The serial interface includes, for example, a serial peripheral interface in which an 8-bit command code and a 24-bit address are standard. [0005] Figure 1A...

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Problems solved by technology

[0014] In this way, when the start address is an even-numbered address, the update of the data bus 30 can be fixed, but in the case of an odd-numbered address, as Figure 4B As shown, the even-numbered address data of DATA1 must be discarded, and the even-numbered address data of DATA2 must be read later, so the period between pulses P1 and P2 of the column selection signal CSL_EN is shortened, and the internal timing margin (timing margin) is reduced, resulting in a high clock frequency action produces bounds

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