A transistor, clamping circuit and integrated circuit
A clamp circuit and field effect transistor technology, applied in the fields of transistors, clamp circuits and integrated circuits, can solve the problems of inability to balance electrostatic protection capability and leakage control, and achieve ESD protection capability, reduce leakage, and reduce sub-radiation. Effect of Threshold Leakage
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Embodiment 1
[0046] In this embodiment, a metal oxide semiconductor field effect transistor is provided, such as image 3 shown, including:
[0047] A substrate 1, an oxide layer 2 on the substrate 1, a silicon layer 3 on the oxide layer 2;
[0048] A source region 4 and a drain region 5 are arranged on the silicon layer 3, and a channel region 6 is formed between the source region 4 and the drain region 5, wherein the source region 4 and the drain region 5 are both heavy doping of the first doping type;
[0049] Polysilicon 7 is disposed on the channel region 6, and the polysilicon 7 is the gate of the metal oxide semiconductor field effect transistor, wherein the first end region 71 of the gate is of the first doping type. heavily doped, the region of the gate except the first end region 71 is heavily doped with a second doping type, and the first doping type is different from the second doping type , the first end region 71 is a region of the gate close to the drain region 5 .
[00...
Embodiment 2
[0060] This embodiment provides a clamping circuit, such as Figure 4-6 As shown, the clamping circuit includes a metal oxide semiconductor field effect transistor 401, and the metal oxide semiconductor field effect transistor 401 includes:
[0061] a substrate, an oxide layer on the substrate, a silicon layer on the oxide layer;
[0062] A source region and a drain region are arranged on the silicon layer, and a channel region is formed between the source region and the drain region, wherein both the source region and the drain region are heavily doped with the first doping type miscellaneous;
[0063] Polysilicon is provided on the channel region, and the polysilicon is the gate of the metal-oxide semiconductor field effect transistor, wherein the first end region of the gate is heavily doped with the first doping type , the region of the gate except for the first end region is heavily doped with a second doping type, the first doping type is different from the second dopi...
Embodiment 3
[0072] This embodiment provides a silicon SOI integrated circuit on an insulating substrate, the circuit includes the clamping circuit for electrostatic protection described in the second embodiment, and the clamping circuit includes the metal oxide described in the first embodiment An object semiconductor field effect transistor, the metal oxide semiconductor field effect transistor comprising:
[0073] a substrate, an oxide layer on the substrate, a silicon layer on the oxide layer;
[0074] A source region and a drain region are arranged on the silicon layer, and a channel region is formed between the source region and the drain region, wherein both the source region and the drain region are heavily doped with the first doping type miscellaneous;
[0075] Polysilicon is provided on the channel region, and the polysilicon is the gate of the metal-oxide semiconductor field effect transistor, wherein the first end region of the gate is heavily doped with the first doping type...
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