DC bias regulator for cascode amplifier

Abstract

An amplifier having a pair of transistors arranged in a cascode amplifier arrangement serially connected to a first voltage source. A DC bias regulator is provided having: a DC bias circuit for producing a reference voltage at a control electrode of a first one of the pair of transistors: and a voltage combiner having a pair of inputs, a first of the pair of inputs being coupled to the reference voltage and a second one of the pair of inputs being coupled to the first voltage source. The DC bias regulator produces a DC bias voltage at a control electrode of a second one of the pair of transistors related to a combination of the reference voltage and the first voltage source.

Description

technical field [0001] The present disclosure relates generally to cascode amplifiers and, more particularly, to DC bias regulators for cascode amplifiers. Background technique [0002] Cascode amplifiers may be formed using field effect transistors (FETs) or bipolar junction transistors (BJTs), as is known in the art. In the case of a FET, the gate is used as a control electrode for controlling the flow of carriers between the source and drain electrodes, and in the case of a BJT, the base is used as a control electrode to control the flow of charge carriers between the source and drain electrodes. and the flow of carriers between the drain. Therefore, it should be noted that although a FET cascode amplifier is described, this material could be equally applied to a BJT. Therefore, the gate electrode of the FET is equivalent to the base electrode of the BJT; referred to herein as the control electrode of the transistor. In a similar manner, the terms drain and source for ...

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Problems solved by technology

However, this DC bias regulator is a passive DC bias regulator circuit and therefore does not provide compensation for manufacturing process, temperature and external DC bias voltage variations

Two Active DC Bias Regulators in U.S. Patent Nos. 5,506,544 to Staudinger et al., entitled "Bias Circuit for Depletion ModeField Effect Transistors," issued April 9, 1996 and June 14, 2011 Described in U.S. Patent No. 7,961,049 to Busking et al., titled "Amplifier with compensated gate bias"; although these two DC bias regulators do compensate for variations in process conditions, they are specific to common source FETs , and are used to maintain a constant drain current through a single FET, not for cascode amplifiers with a pair of FETs

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