Control code latch circuit and clock data recovery circuit

Abstract

The invention provides a control code latch circuit, which comprises a shifting register, a NOR gate, a control code balance point judgement circuit, a de-twitter circuit and a latch, wherein the input end of the NOR gate is connected with the output end of the shifting register and is used for outputting a locking judgment signal Lock; the input end of the control code balance point judgement circuit is connected with the output end of the shifting register; the reset end of the control code balance point judgement circuit is connected with the output signal Lock of the NOR gate and outputs asignal Load; the de-twitter circuit is used for outputting a latch control signal Load-en after de-twitter; and the latch is used for latching the input phase control code PI-Code [k-1: 0]. The invention further provides a clock data recovery circuit, which comprises a control code latch circuit. The control code latch circuit and the clock data recovery circuit are simple in structure and strongin transportability; a format conversion circuit is not needed to add; the time delay is greatly reduced; relatively high working frequency is facilitated to reach; relatively good jitter function isrealized; and meanwhile, the loop bandwidth, the loop tracking capability and the jitter tolerance range are greatly improved.

Description

technical field [0001] The invention relates to the technical field of high-speed data transmission, in particular to a control code latch circuit and a clock data recovery circuit. Background technique [0002] Clock and Data Recovery (CDR) circuits based on Phase Interpolation (PI) are widely used in high-speed data transmission, and digital control logic is used to replace analog charge pumps and loop filters to achieve convenient control and in-process Flexible conversion between. figure 1 Shown is an existing digital PI-CDR structure, taking the quarter-rate mode as an example. The serial data Din is input by a differential channel 101, and passes through a Continuous Time Linear Equalizer (Continues Time Linear Equalizer, CTLE) 102 to output equalized data Din'. The unit 103 is a phase locked loop (Phase Lock Loop, PLL), and the generated 8-phase clock CLK is converted into a phase-adjustable clock by a 4-way phase interpolation module (PI) 104 . Unit 105 is a binar...

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Problems solved by technology

Therefore, the circuit needs to convert the control code format, which increases the area overhead and greatly increases the delay.

[0012] (2) The realization of the existing control code latch circuit requires a k+1-bit subtractor, which is implemented by a look-ahead adder. In order to achieve the required frequency, the consumption area is relatively large, and with the increase of k, the delay will decrease more difficult to control

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