ldmos device with array electrostatic protection structure

Abstract

The invention discloses an LDMOS device with an array electrostatic protection structure. The LDMOS device comprises a P+ substrate layer, a P- epitaxial layer, a P+ injection layer, a P well region,a drift region, a under-gate oxide layer, a gate electrode, a source electrode, a source field oxide layer, a drain electrode, back metal, source deep trench interconnect metal, and a source field plate array comprising a plurality of parallel source field plates having equal length and width. The source field plates are disposed in a direction perpendicular to the gate electrode. One end of eachsource field plate is connected to the source electrode. The other end of each source field plate is connected to the source field plate oxide layer across the gate electrode. The field plate structure of the source region extends the source region between the gate and the drain and enables the source region to be arranged in an array. On the one hand, the gate-drain side is divided so that the peak electric field of the under-gate drain side and the under-gate source side are uniformly distributed and external transient high voltage can be absorbed. On the other hand, due to the array distribution, the current carrying capacity is maximized and the effect of a power device is realized.

Description

technical field [0001] The invention relates to an LDMOS device with an array electrostatic protection structure. Background technique [0002] LDMOS is a radio frequency power device with a lateral double diffusion structure. Compared with ordinary power MOS devices, LDMOS devices have a lightly doped drift region near the gate side to bear the high voltage of device operation. There is a high electric field on the surface of the drift region near the gate, which causes the device to break down first near the high electric field. Compared with ordinary MOS devices, LDMOS has a quasi-saturation effect and a negative resistance effect under high power conditions. Because of these structural characteristics of LDMOS, compared with bipolar transistors, it has obvious advantages such as high linearity, high gain, good temperature stability, high standing wave mismatch ratio, and simple bias circuit. Therefore, LDMOS is widely used in radio frequency amplifiers, such as pulsed r...

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Problems solved by technology

[0004] Document CN102790047A discloses a ggnmos device and its manufacturing method. A dummy gate structure is inserted in series between the upper nMOS and the lower nMOS for isolation. By controlling the voltage of the dummy gate, the breakdown voltage can be adjusted within an appropriate range. The transistor nMOS and the lower transistor nMOS are connected to the gate and the source of the lower transistor nMOS, making a diode mode, that is, the upper and lower sides of the field effect transistor controlled by the virtual gate are connected in series with a transistor mode clamping diode. It makes its series conduction voltage and impedance rise, increases power consumption, reduces power density, limits the effective transmission of signals, and increases the distortion of signal transmission; and the source region of the upper nMOS and the drain of the lower nMOS pass through the electrical Short circuit connection, resulting in very limited control function of the virtual gate. Compared with the basic functions of general field effect transistors, the control function of this device is limited, which is not conducive to the needs of circuit design.

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