3D NAND memory and preparation method thereof

Abstract

The invention provides a 3D NAND memory and a preparation method thereof. The 3D NAND memory comprises a substrate and a stacked layer formed on the substrate, wherein the stacked layer comprises a plurality of gate layers, a plurality of channel holes, channel layers, a plurality of gate line separation troughs, first air gaps and / or second air gaps; the plurality of gate layers are sequentiallyarranged along the thickness direction of the substrate; the plurality of channel holes are formed in the stacked layer and are vertical to the substrate; the channel layers are formed in the corresponding channel holes; the plurality of gate line separation troughs are formed in the stacked layer and divide the stacked layer into a plurality of stacked layer subblocks; one first air gap is located between two adjacent gate layers; and the second air gaps are located in the corresponding gate line separation troughs. The preparation method of the 3D NAND memory provided by the invention is simple in step and strong in operability, capacitive coupling between gates of the prepared memory is effectively reduced, mutual interference between the gates is reduced and the performance of the memory is more excellent.

Description

technical field [0001] The invention relates to the field of three-dimensional semiconductor memory, in particular to the field of three-dimensional NAND type memory. Background technique [0002] In order to meet the development of high-efficiency and low-cost microelectronics industry, semiconductor memory devices need to have higher integration density. Regarding semiconductor memory devices, because their integration density is very important in determining product prices, that is, high-density integration is very important. For traditional two-dimensional and planar semiconductor storage devices, because their integration density mainly depends on the unit area occupied by a single storage device, the integration degree is very dependent on the quality of photolithography and masking process. However, even if expensive process equipment is continuously used to improve the precision of lithography and mask processes, the improvement of integration density is still very ...

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Problems solved by technology

[0004] At present, 3D NAND memory has been successfully introduced into commercial applications, but in the existing 3D NAND memory, the coupling between the gate and the gate is the cause of wrong writing, driving voltage offset and reduced driving voltage distribution during the programming process. At the same time, the parasitic capacitance between the gate line and the gate line (also called the word line) will also interfere with programming and reading, resulting in a decrease in programming and reading speed

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