Normalized bridge capacitance conversion circuit with calibration

Abstract

With a calibration-type normalized bridge capacitor conversion circuit, including bridge capacitors and low N-bit capacitor arrays and high M-bit capacitor arrays composed of data bit capacitors, the capacitance values ​​of all data bit capacitors are integer multiples of the unit capacitor value. The multiple corresponds to the weight value of its data bit, and the low N-bit capacitor array is only composed of N low-bit capacitors, and each low-bit capacitor corresponds to a data bit; the capacitance value of the bridge capacitor is 1 unit capacitance value; the bridge capacitor and The data bit capacitance is composed of X independent unit capacitances, X is a natural number, and the value is determined by the location of the capacitance. The capacitance value of each unit capacitance is 1 unit capacitance value; in the high-M bit capacitance array, each capacitance are paired with a trimming array, N‑X≤10. The invention ensures that the entire charge redistribution capacitor array is a unit capacitor, and at the same time adds a capacitor trimming array to the high X bits to ensure that the precision of the final finished circuit meets the precision requirement of 12 bits or above.

Description

technical field [0001] The invention relates to an integrated circuit, in particular to an A / D converter circuit of more than 12 bits with high precision and low power consumption. Background technique [0002] SAR ADC is the classic design scheme of the current mainstream high-precision A / D converter, and its core units are high-precision DAC core, comparator, digital logic and other units. Its static power consumption is mainly concentrated in the DAC core and comparator unit. In order to reduce static power consumption, its DAC core is mostly completed by a capacitor redistribution array, and its conversion accuracy is mainly determined by the internal DAC core unit. [0003] It can be seen from the above that the capacitor redistributed SAR ADC is currently the mainstream low-power, high-precision A / D converter design scheme, and the internal capacitor redistributed array is the core unit that affects the overall ADC conversion linearity. For N-bit SAR ADC, the classic ...

AI Technical Summary

Problems solved by technology

[0006] Generally, when a process manufacturer manufactures a capacitor array, if all capacitors are unit capacitors, the size of each capacitor and the surrounding environment are completely consistent, the resulting capacitor array has a high matching (the natural matching degree can be higher than 0.1%, and the matching accuracy is about the same as However, if there are non-unit capacitors with inconsistent sizes in the capacitor array, the matching of the capacitor array in the finished product is poor due to the inconsistency of the size of the individual capacitors and the surrounding environment (the natural matching accuracy can be lower than 20%)

[0007] In summary, figure 2 Although the segmented capacitor array shown can effectively reduce the number of capacitors used, the bridging capacitors introduced are not the same size as the other unit capacitors in the array, so the bridge capacitors usually have a large mismatch after the finished product is manufactured in the craft factory. , and the natural matching accuracy of unit capacitance is about 10 bits, for 12-bit and above precision ADCs, it is necessary to optimize figure 2 The structure shown, otherwise it cannot meet the application requirements of 12-bit and higher precision

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