A kind of asynchronous fifo realization circuit

Abstract

The invention discloses an asynchronous fifo implementation circuit. The circuit comprises a fifo control module, and clk1-based synchronous fifo1 and clk2-based synchronous fifo2 set based on asynchronous clocks clk1 and clk2; the data widths in the synchronous fifo1 and the synchronous fifo2 are the same; the fifo control module comprises an fifo1 state control module interacting with the clk1-based synchronous fifo1, an fifo2 state control module interacting with the clk2-based synchronous fifo2, and a cross-clock-domain pulse conversion module; the fifo1 state control module and the fifo2state control module are used for carrying out state control on the synchronous fifo1 and the synchronous fifo2 according to input signals of the circuit respectively; the state control comprises an IDLE state, a WR state and an RD state; and the cross-clock-domain pulse conversion module is used for converting a pulse signal between a clk1 clock domain and a clk1 clock domain.

Description

technical field [0001] The invention relates to the field of hardware circuit design, in particular to an asynchronous fifo implementation circuit. Background technique [0002] In hardware design, fifo is generally used for the transmission of large amounts of data. For a synchronous fifo whose data is written and read in the same clock domain, a synchronous dual-port RAM or register can be used; for an asynchronous fifo whose data is written and read in different clock domains, an asynchronous dual-port RAM is generally used. For commonly used process libraries, such as ASIC / SOC implementation process libraries, and FPGA and CPLD basic unit libraries, most of them do not have asynchronous dual-port RAM, or the RAM capacity does not match the design requirements, which directly limits the flexibility of the design. Other designs complete the required functions. [0003] In the prior art, the Chinese patent "Universal Asynchronous FIFO Module Storage Method" with the publi...

AI Technical Summary

Problems solved by technology

For commonly used process libraries, such as ASIC / SOC implementation process libraries, and FPGA and CPLD basic unit libraries, most of them do not have asynchronous dual-port RAM, or the RAM capacity does not match the design requirements, which directly limits the flexibility of the design. Other design solutions to complete the required functions

[0003] In the prior art, the Chinese patent "Universal Asynchronous FIFO Module Storage Method" with the publication number CN 102866874A solves the problem that the existing asynchronous FIFO module cannot use the IP core of the D latch storage structure fifo, but the method When reading and writing FIFO each time, it is necessary to judge the read and write address relationship under different clock domains, which directly leads to slow reading and writing speed of asynchronous FIFO; the Chinese patent with publication number CN1478226 "Low waiting time FIFO circuit for hybrid asynchronous synchronous system" , through the control of the storage unit, the problem of slow reading and writing speed of FIFO is solved, but the circuit logic is complicated and the versatility is poor; the Chinese patent "Data caching method of asynchronous double FIFO based on FIFO" with the application number CN200810159783.2, designed The asynchronous dual FIFO has strict requirements on the continuity and segmentation of receiving and sending, and has poor versatility; the Chinese patent "Double-ended dual-channel FIFO with synchronous and asynchronous conversion" with the publication number CN 102253916A adopts a fixed address mechanism for asynchronous reading and writing. Practical application related, poor versatility

However, they are all limited by the process library, and there are still problems of complex circuit logic and poor versatility

Images