Unlock instant, AI-driven research and patent intelligence for your innovation.

Stacked chip package method and package structure

A chip packaging structure and chip packaging technology, applied in the manufacturing of electrical components, electrical solid-state devices, semiconductor/solid-state devices, etc. Effect of facet area

Pending Publication Date: 2018-11-16
CHINA WAFER LEVEL CSP
View PDF7 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although the above scheme can be used for multi-chip integration, the chips in the same plane greatly increase the plane area of ​​the entire packaging structure, which is not conducive to the miniaturization of chip packaging.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Stacked chip package method and package structure
  • Stacked chip package method and package structure
  • Stacked chip package method and package structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0069] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0070] It should be noted that the purpose of providing these drawings is to facilitate the understanding of the embodiments of the present invention, and should not be construed as an improper limitation of the present invention. For clarity, the dimensions shown in the figures are not drawn to scale and may be enlarged, reduced or otherwise changed. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual pr...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The present invention provides a stacked chip package method and a package structure. The method comprises the steps of: providing a first chip, wherein the surface of the first chip is provided witha blank area; providing a second chip, wherein the second chip is a flip chip; and performing flip package of the second chip to the blank area of the first chip. The stacked chip package method and the package structure package the second chip into the blank area of the first chip, and the stacked package fully utilizes the blank area of the back surface of the first chip to reduce the plane areaof the package structure and achieve the miniaturization of the packaged plane area.

Description

technical field [0001] The invention belongs to the technology in the field of semiconductor manufacturing, and in particular relates to a stacked chip packaging method and packaging structure. Background technique [0002] With the trend of multi-function and miniaturization of electronic products, high-density microelectronic assembly technology has gradually become the mainstream in the new generation of electronic products. In order to cooperate with the development of the new generation of electronic products, the size of the chip is developing in the direction of higher density, faster speed, smaller size and lower cost. [0003] At present, Wafer Level Chip Size Packaging (WLCSP) usually distributes the solder pads arranged on the periphery of the semiconductor chip into a large number of metal solder balls arranged in an area array through a redistribution process. Metal solder balls are also called Solder bumps. Since wafer-level chip size packaging is first packa...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768H01L23/538
CPCH01L23/5386H01L21/76895
Inventor 谢国梁
Owner CHINA WAFER LEVEL CSP