Test method for interface state density and capture cross-section between semiconductors
An interface state density and trapping cross section technology, applied in the field of semiconductors, can solve the problems affecting the accuracy of the interface state density distribution test results, unable to obtain the change of the trapping cross section with the energy level position distribution, etc. , the test results are accurate
Inactive Publication Date: 2018-12-21
ZHEJIANG UNIV
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Problems solved by technology
[0006] However, the relevant measurement techniques widely used at present, including high-low frequency C / V test and deep energy level transient spectrum test, cannot obtain the change of capture cross section with the position distribution of energy level, but use a constant capture cross section
Obviously, this does not correspond to the actual situation
And this will further affect the accuracy of the interface state density with energy and distribution test results
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Embodiment 1
[0035] (1) By chemical vapor phase epitaxy, a p+ silicon film with a thickness of 10 μm is epitaxially grown on the surface of a p-type silicon wafer with a thickness of 600 μm and a resistivity of 2Ω.cm. The corresponding energy band diagram is as figure 1 As shown, the upper and lower figures correspond to the energy band conditions at zero bias and bias V>0 respectively, where Ec is the top of the conduction band, Ev is the bottom of the valence band, and E F is the Fermi level. It can be seen from the figure that by applying a forward pulse voltage on the gold film, charges can be injected into the grain boundaries and fill the donor states. The non-equilibrium holes in the state need to relax by emitting holes at zero bias.
[0036] (2) The surface evaporation area of the p+ silicon thin film grown on the above-mentioned homojunction by thermal evaporation is 1mm 2 , a gold film with a thickness of 100nm, using DLTS to test the transient capacitance at different temp...
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Abstract
The invention discloses a test method for interface state density and a capture cross-section between semiconductors. The method comprises the steps that (1) a homogeneous or heterogeneous semiconductor thin film is grown on the surface of a semiconductor slice, and then a homogeneous or heterogeneous junction is formed; (2) after a metal thin film is grown on the homogeneous or heterogeneous junction, capacitor transient testing is performed under different test temperatures T, changes of a capacitor in the current carrier emitting process are obtained, and the capacitor is converted into a transient capacitor with a load N<it>; (3) the load N<it> is derived about time t, and emission rates e of the load under the different test temperatures are solved; and (4) under different load intensities, a function of ln(e / T<2>) about 1 / T is made, and distribution of the interface state density and the capture cross-section along with an energy level is solved through a slope and an intercept respectively. By use of the test method, distribution of the capture cross-section and the interface state density along with the position of the energy level can be acquired, and application iswide.
Description
technical field [0001] The invention belongs to the technical field of semiconductors, in particular to a method for testing interface state density and capture cross section between semiconductors. Background technique [0002] As the size of silicon wafers continues to increase, there will be native defects in 8-inch and 12-inch silicon, which will reduce the yield of devices; at the same time, as the line width of devices decreases year by year, the requirements for silicon wafers are increasing year by year, so epitaxy Silicon wafers are used to improve the yield and quality of large-sized chips because they can avoid native defects. [0003] However, the interface in the epitaxial silicon wafer will also have interface defects, which will act as the recombination center of carriers, resulting in an increase in leakage current, thereby increasing the noise signal of silicon-based devices at low frequencies in semiconductor devices, and even leading to integration failur...
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IPC IPC(8): G01R31/26
CPCG01R31/2601
Inventor 余学功胡泽晨董鹏杨德仁
Owner ZHEJIANG UNIV