Method for forming ladder structure for double-sided wiring of three-dimensional memory device
A technology of storage devices and ladder structures, applied in semiconductor devices, electrical solid state devices, semiconductor/solid state device components, etc., can solve problems such as high cost
Active Publication Date: 2019-09-03
YANGTZE MEMORY TECH CO LTD
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Problems solved by technology
However, as the feature size of memory cells approaches the lower limit, planar processing and fabrication techniques become challenging and costly
As a result, the storage density of planar memory cells approaches the upper limit
Method used
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[0016] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the relevant art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure can also be used in a variety of other applications.
[0017] It is noted that references in the specification to "one embodiment," "an embodiment," "exemplary embodiment," "some embodiments," etc. indicate that the described embodiments may include a particular feature, structure, or characteristic, but Not every embodiment may include that particular feature, structure or characteristic. Furthermore, such phrases are not necessarily referring to the same embodiment. In addition, when a particular feature, structure or characteristic is described in connection with an embodim...
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Embodiments of a method for forming a ladder structure for double-sided wiring of a three-dimensional (3D) memory device are disclosed. In an example, a first dielectric layer is formed on the substrate, and a first photoresist layer is formed on the first dielectric layer. A recess through the first dielectric layer to the substrate is patterned by a cycle consisting of trim-etching the first dielectric layer. A plurality of dielectric / sacrificial layer pairs are formed filling the recess. A second photoresist layer is formed on the top surface of the dielectric / sacrificial layer pair. The dielectric / sacrificial layer pair is patterned by a cycle consisting of trim-etching the dielectric / sacrificial layer pair. A second dielectric layer is formed overlying the patterned dielectric / sacrificial layer pair. A memory stack layer comprising a plurality of conductor / dielectric layer pairs is formed on the substrate by replacing a sacrificial layer in the patterned dielectric / sacrifice layer pair with a plurality of conductor layers.
Description
Background technique [0001] Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and methods of manufacturing the same. [0002] Planar memory cells can be scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and fabrication techniques. However, as the feature size of memory cells approaches the lower limit, planar processing and fabrication techniques become challenging and costly. As a result, the storage density of planar memory cells approaches the upper limit. [0003] 3D memory architectures can address density limitations in planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. Contents of the invention [0004] Embodiments of a method for manufacturing a ladder structure for wiring on both sides of a 3D memory device are disclosed herein. [0005] In one example, a method for forming a 3D memory ...
Claims
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IPC IPC(8): H01L27/11578H10B10/00H10B43/20H10B43/10H10B43/27H10B43/35
CPCH10B43/20H10B43/10H10B43/50H10B43/27H01L23/5226H01L23/528H10B43/35
Inventor 肖莉红胡禺石
Owner YANGTZE MEMORY TECH CO LTD