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Non-volatile memory sub-block erasure disturb management scheme

A non-volatile, memory unit technology, applied in static memory, memory system, read-only memory, etc.

Active Publication Date: 2019-01-01
WESTERN DIGITAL TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] As the density of memory structures increases, maintaining the integrity of stored data becomes more challenging

Method used

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  • Non-volatile memory sub-block erasure disturb management scheme
  • Non-volatile memory sub-block erasure disturb management scheme
  • Non-volatile memory sub-block erasure disturb management scheme

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Experimental program
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Embodiment Construction

[0027] Data stored in nonvolatile memory may degrade over time. This may be due to several reasons, such as charge leakage in the memory cell whose data state is based on the stored charge level. Data degradation on one memory cell may be caused by memory operations on other memory cells. For example, reading or writing data in one memory cell places stress on nearby memory cells, which can cause read or write "disturbance" to these nearby memory cells, which read or write "disturbance" ” may change their data state. Erase operations may also cause erase disturb to nearby non-erased memory cells.

[0028] For example, in a two-dimensional array of charge storing nonvolatile memory cells, an erase operation on a block of memory cells typically involves setting the control gates of the memory cells of the block to low voltage or ground, and setting the A high erase voltage is applied to the well structure beneath the array, thereby removing the charge stored in the memory cel...

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Abstract

A non-volatile memory is configured to allow programming and erase at the sub-block level. In a sub-block erase, some of the memory cells can be selected for erase while others are not selected for erase, such as by leaving their word lines to float while applying the erase voltage to the well structure of the physical block to which the sub-blocks belong. Although a sub-block erase applies a lower electric field across the non-selected memory cells than the erase selected memory cells, it still places the non-selected memory cells under some degree of stress and can lead to erase disturb. Tohelp manage this erase disturb, each sub-block has an associated erase disturb count, which is incremented when another sub-block of the same physical block is erased, but reset when the sub-block itself is erase. Once a count reaches a threshold value, the sub-block can be marked for remedial action, such as refresh or garbage collection.

Description

technical field [0001] The present invention relates to semiconductor memories, and methods of managing subblock erase disturbances for semiconductor memories. Background technique [0002] Semiconductor memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid state drives, non-mobile computing devices, and others. Semiconductor memory may include nonvolatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source, such as a battery. [0003] As the density of memory structures increases, maintaining the integrity of the stored data becomes more challenging. Contents of the invention [0004] In one example, a device includes a plurality of non-volatile memory cells formed over a shared well region. The memory cells include a first set o...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/34
CPCG11C16/3431G11C11/5628G11C16/0483G11C16/10G11C16/16G11C16/3445G11C16/3459G11C16/349G11C11/5635G06F12/0253
Inventor 胡信德
Owner WESTERN DIGITAL TECH INC