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A wafer structure and a processing method thereof

A processing method and wafer technology, applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., can solve problems affecting the reliability of devices, generating stress, destroying the structure and morphology of chip regions, etc., to prevent damage, The effect of protecting the chip area and improving the reliability of the device

Inactive Publication Date: 2019-01-15
SHENGSHIYAOLAN SHENZHEN TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When scribing, during the process of cutting the scribing lane area, stress will be generated, which will destroy the structure and morphology of the chip area and affect the reliability of the device.

Method used

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  • A wafer structure and a processing method thereof
  • A wafer structure and a processing method thereof
  • A wafer structure and a processing method thereof

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Embodiment Construction

[0024] The preferred embodiments of the present invention will be described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0025] In describing the present invention, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "border", "both sides", The orientation or positional relationship indicated by "inner", "outer", "interval" and so on is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating...

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Abstract

The invention relates to a wafer structure and a processing method thereof, the wafer includes a chip region and a scribe track region, A chip region includes a cell region, a partial pressure ring region and a cut-off ring region, The cell region is located at the center of the chip region, the voltage dividing ring region is located between the cell region and the cut-off ring region, and the scribe track region is located between adjacent two cut-off ring regions and communicated with each other, and is etched at the boundary of two sides of the scribe track region of the wafer to form a discontinuous distribution and the grooves on both sides are spaced apart, and the groove depth is 1- 1.5 um, and that groove is fil with photosensitive polyimide. After the wafer is fabricated, the stress generated when the power device is formed by cutting the sliced region will not destroy the chip structure, and the reliability of the device is improved.

Description

technical field [0001] The invention relates to the field of semiconductor technology, in particular to a wafer structure and a processing method thereof. Background technique [0002] Power semiconductor devices include vertical double diffused metal oxide semiconductor (VDMOS), fast recovery diode (FRD), Schottky diode, transient voltage suppressor (TVS), etc. In order to reduce the cost, it is hoped that the size of the device should be as small as possible while ensuring sufficient current driving capability and breakdown voltage. Power semiconductor devices are produced from wafers. The wafer layout includes two areas: the chip area and the scribe area. The chip area is the area occupied by the power semiconductor device. The scribe area is used to place the Wafers are diced into areas of power semiconductor devices one by one. During scribing, during the process of cutting the scribing lane area, stress will be generated, which will destroy the structure and morpholo...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/78H01L29/06H01L23/544
CPCH01L21/78H01L23/544H01L29/06H01L2223/54453
Inventor 不公告发明人
Owner SHENGSHIYAOLAN SHENZHEN TECH CO LTD
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