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A method for reducing wafer bonding alignment misalignment

A technology of alignment deviation and wafer bonding, which is applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of low efficiency and low alignment accuracy, achieve high experimental efficiency, improve alignment accuracy, The effect of simple steps

Inactive Publication Date: 2019-01-18
NO 55 INST CHINA ELECTRONIC SCI & TECHNOLOGYGROUP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The present invention proposes a method for reducing the alignment deviation of wafer bonding, and its purpose is to address the defects of low alignment accuracy and low efficiency in BCB bonding between wafers in the prior art, and proposes an operation Simple, high-accuracy method for reducing misalignment in wafer bonding

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  • A method for reducing wafer bonding alignment misalignment
  • A method for reducing wafer bonding alignment misalignment
  • A method for reducing wafer bonding alignment misalignment

Examples

Experimental program
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Embodiment 1

[0038] A method for reducing wafer bonding misalignment, comprising the steps of:

[0039] 1) A layer of patterned patterned metal 003 is formed on the surface of wafer 001 by evaporation or electroplating. The patterned metal 003 is gold with a thickness of 0.75 microns;

[0040] 2) Form a layer of low melting point metal 004 with the same pattern as the patterned metal 003 on the surface of the wafer 002 by evaporation or electroplating. The metal 004 is indium with a thickness of 1.5 microns;

[0041] 3) Spin-coat a layer of BCB on the surface of wafer 001, BCB completely covers the patterned metal 003, and the thickness of BCB is 2.0 microns;

[0042] 4) Put the wafer 001 into the oven, and perform soft curing on the BCB on its surface. The curing temperature is 165 degrees Celsius and the time is 1.5 hours;

[0043] 5) After the BCB on the surface of the wafer 001 is soft-cured, perform patterned dry plasma etching on the BCB. The etching pattern is the same as that of t...

Embodiment 2

[0046] A method for reducing wafer bonding misalignment, comprising the steps of:

[0047] 1) A layer of patterned patterned metal 003 is formed on the surface of wafer 001 by evaporation or electroplating. The patterned metal 003 is copper with a thickness of 0.85 microns;

[0048] 2) Form a layer of low melting point metal 004 with the same pattern as patterned metal 003 on the surface of wafer 002 by evaporation or electroplating. Metal 004 is indium with a thickness of 1.65 microns;

[0049] 3) Spin-coat a layer of BCB on the surface of wafer 001, BCB completely covers the patterned metal 003, and the thickness of BCB is 1.85 microns;

[0050] 4) Put the wafer 001 into the oven, and perform soft curing on the BCB on its surface. The curing temperature is 175 degrees Celsius and the time is 1.3 hours;

[0051] 5) After the BCB on the surface of the wafer 001 is soft-cured, perform patterned dry plasma etching on the BCB. The etching pattern is the same as that of the patte...

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Abstract

The invention relates to a method for reducing wafer bonding alignment misalignment, comprising: 1) forming a layer of patterned metal on the surface of A wafer by evaporation or electroplating; 2) for a layer of low mel point metal with that same pattern as the patterned metal on the surface of the B wafer by evaporation or electroplating; 3) spin coat a layer of BCB on that surface of the A waf;4) softly cure that BCB on the surface of the A wafer; 5) carry out patterned dry etch on that BCB on the surface of the A wafer until the BCB on the patterned metal surface is etched clean; 6) A wafand B wafer face each other face to face, align by alignment mark, raise pressure, in order to realize metal and BCB bonding. That advantage: adopting low melting point metal pre-bonding reinforcement method, reduce the problem of alignment deviation caused by BCB flow when wafer bonding, and improve the alignment accuracy of BCB bonding between wafers.

Description

technical field [0001] The invention relates to a method for reducing wafer bonding alignment deviation, which belongs to the technical field of semiconductor technology. Background technique [0002] With the continuous improvement of chip integration and the increase of CMOS process complexity, the cost and performance of integrated circuits have become more and more prominent, and three-dimensional integration technology has become a research hotspot. The three-dimensional integrated circuit is different from the two-dimensional CMOS integration process, which only has a single active layer, but has multiple active layers stacked in the vertical direction. The signal is mainly transmitted by using a through-silicon hole structure, so that devices of different layers are on the shortest path. A global interconnection is achieved. In three-dimensional integration, bonding technology provides electrical connection and mechanical support for chip stacking, thereby realizing ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/18H01L21/68
CPCH01L21/187H01L21/68
Inventor 吴立枢戴家赟孔月婵
Owner NO 55 INST CHINA ELECTRONIC SCI & TECHNOLOGYGROUP CO LTD