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A method and device for processing clock signals

A clock signal and reference clock signal technology, applied in the direction of electrical components, power oscillators, etc., can solve the problems affecting the phase noise of the clock signal output signal, the deterioration of the spectral purity of the output signal, and the inability to filter out harmonic spurs, etc., to improve Stability and signal-to-noise ratio, elimination of additional phase noise, effects of spurious suppression

Pending Publication Date: 2019-01-25
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, using the internal phase-locked loop as the reference clock of the clock signal will generate additional phase drift due to the phase-locked loop frequency multiplier circuit, which directly affects the phase noise of the output signal of the clock signal source
In addition, the use of passive filters cannot filter out harmonic spurs, resulting in the deterioration of the spectral purity of the output signal of the clock signal source, thereby affecting the stability and signal-to-noise ratio of the clock signal source

Method used

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  • A method and device for processing clock signals
  • A method and device for processing clock signals
  • A method and device for processing clock signals

Examples

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no. 1 example

[0043] In the first embodiment of the present invention, a device for processing clock signals, such as figure 1 As shown, the device specifically includes the following components:

[0044] 1) The frequency multiplication module 101 is configured to perform frequency multiplication processing on the signal generated by the rubidium atomic clock according to the set frequency multiplication coefficient to obtain a reference clock signal.

[0045] Specifically, in this embodiment, a rubidium atomic clock is used as the external reference clock of the clock signal source, thereby replacing the internal phase-locked loop used in the prior art as the reference clock of the clock signal source. In this embodiment, it is also necessary to perform frequency multiplication processing on the signal generated by the rubidium atomic clock according to a set frequency multiplication coefficient, and use the frequency multiplication processed signal as a reference clock of the clock signal...

no. 3 example

[0101] In the third embodiment of the present invention, a device for processing clock signals, such as image 3 As shown, the device specifically includes the following components:

[0102] A clock signal generating module 102, configured to generate a clock signal according to a reference clock signal.

[0103] The frequency-selective filtering module 104 is configured to amplify the amplitude of the generated clock signal, and frequency-selectively filter the clock signal at the third set frequency point.

[0104] Specifically, the frequency selection filter module 104 is composed of a field effect transistor and a single tuning circuit.

[0105] The field effect transistor is used for amplifying the amplitude of the clock signal. By adjusting the resistance in the field effect tube, the field effect tube is in a state of amplitude amplification. The larger the resistance value, the greater the magnification.

[0106] The single-tuned circuit is composed of an adjustabl...

no. 4 example

[0129] In the fourth embodiment of the present invention, a method for processing a clock signal, such as Figure 4 As shown, the method specifically includes the following steps:

[0130] Step S401: Perform frequency multiplication processing on the signal generated by the rubidium atomic clock according to the set frequency multiplication coefficient to obtain a reference clock signal.

[0131] Specifically, in this embodiment, a rubidium atomic clock is used as the reference clock of the clock signal source, thereby replacing the internal phase-locked loop used in the prior art as the reference clock of the clock signal source. In this embodiment, it is also necessary to perform frequency multiplication processing on the signal generated by the rubidium atomic clock according to a set frequency multiplication coefficient, and use the frequency multiplication processed signal as a reference clock of the clock signal source. Preferably, in this embodiment, a processing manne...

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Abstract

The invention discloses a method and a device for processing a clock signal. The device comprises a frequency doubling module, which is used for frequency doubling processing the signal generated by arubidium atomic clock according to a set frequency doubling coefficient to obtain a reference clock signal; a clock signal generation module, configured to generate a clock signal according to the reference clock signal. The rubidium atomic clock is used as the external reference clock of the clock signal source, and the signal generated by the rubidium atomic clock is subjected to frequency doubling processing to be used as the reference clock of the clock signal source, thereby replacing the internal phase-locked frequency doubling circuit in the prior art, thereby eliminating the influenceof the additional phase noise caused by the internal phase-locked frequency doubling circuit.

Description

technical field [0001] The present invention relates to the technical field of clock signal sources, in particular to a method and device for processing clock signals. Background technique [0002] With the improvement of the capacity transmission rate of the PTN (Packet Transport Network, packet transport network) bearer equipment, a higher requirement for improving the signal-to-noise ratio is also put forward for the clock performance of the PTN equipment. The clock signal source is a key component of the PTN equipment. The stability of the clock signal source and the signal-to-noise ratio of the clock signal directly affect the performance of the PTN equipment. [0003] The clock signal source in the prior art generally adopts an internal phase-locked loop as a reference clock and uses a common passive filter. However, using the internal phase-locked loop as the reference clock of the clock signal will generate additional phase drift due to the frequency multiplier circ...

Claims

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Application Information

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IPC IPC(8): H03B19/00
CPCH03B19/00
Inventor 程龙
Owner ZTE CORP