System and method for odd modulus memory channel interleaving

Abstract

A system for providing odd modulus memory channel interleaving may include a dynamic random access memory (DRAM) system and a system on chip (SoC). The SoC comprises a first memory controller, a second memory controller, and a symmetric memory channel interleaver. The first memory controller is electrically coupled to a first DRAM module via a first memory bus. The second memory controller is electrically coupled to a second DRAM module and a third DRAM module via a second memory bus. The symmetric memory channel interleaver is configured to uniformly distribute DRAM traffic to the first memory controller and the second memory controller. The first memory controller provides a first interleaved channel to the first DRAM module via the first memory bus. The second memory controller providesa second interleaved channel to the second DRAM module via upper address bits on the second memory bus.

Description

Background technique [0001] Many computing devices, including portable computing devices such as mobile phones, include a system on a chip ("SoC"). SoCs are demanding increased power performance and capacity from memory devices, such as double data rate (DDR) memory devices. These requirements lead to faster clock speeds and wide buses, which are then usually divided into multiple narrower memory channels in order to remain efficient. Multiple memory channels can be address interleaved together to evenly distribute memory traffic across memory devices and optimize performance. Memory data is evenly distributed by assigning addresses to alternating memory channels. This technique is often referred to as symmetric channel interleaving. [0002] Channel interleaving is an efficient and simple way to combine the bandwidth of multiple memory channels to provide higher overall bandwidth while keeping the individual channel widths to manageable sizes. Interleaving between two lan...

AI Technical Summary

Problems solved by technology

For example, four memory channels provide an increased level of total bandwidth compared to two memory channels, but at the expense of increased SoC die area

While three memory channels can provide a moderate level of total bandwidth with a slight increase in SoC die, three-way interleaving involves added complexity

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