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Array substrate and manufacture method thereof, and display panel

A technology of array substrate and manufacturing method, which is applied in nonlinear optics, instrumentation, optics, etc., and can solve problems such as large gate drive circuit loads

Inactive Publication Date: 2019-03-19
HKC CORP LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In order to solve the problem of excessive load on the gate drive circuit, the object of the present invention is to provide an array substrate, a display panel and a method for manufacturing the array substrate

Method used

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  • Array substrate and manufacture method thereof, and display panel
  • Array substrate and manufacture method thereof, and display panel
  • Array substrate and manufacture method thereof, and display panel

Examples

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Embodiment Construction

[0026] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the associated drawings. A preferred embodiment of the invention is shown in the drawings. However, the present invention can be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present invention will be thorough and complete.

[0027] It should be noted that when an element is considered to be "connected" to another element, it may be directly connected to and integrally integrated with the other element, or there may be an intervening element at the same time. The terms "mounted", "one end", "the other end" and similar expressions are used herein for the purpose of description only.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of or...

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Abstract

The invention relates to an array substrate and a manufacture method thereof, and a display panel. The array substrate includes a first substrate, a first conductive layer, a first passivation layer,a second conductive layer, a second passivation layer, a first electrode layer, a liquid crystal layer, a second electrode layer and a second substrate arranged sequentially from bottom to top. The first substrate is partially covered with the first passivation layer, and the first passivation layer is partially covered with the second passivation layer, and the first conductive layer, the first passivation layer, the second conductive layer and the second passivation layer are partially covered with the first electrode layer; the first conductive layer includes multiple first wires, and the second conductive layer includes multiple second wires corresponding to the first wires, wherein the first wires are connected with the corresponding second wires through the corresponding wires of thefirst conductive layer. Each first wire is provided with a target region, the projections, on the corresponding first wires, of the second wires are located in the corresponding target regions, and the load of a gate driving circuit and the capacitance between plates are reduced.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to an array substrate, a display panel and a manufacturing method of the array substrate. Background technique [0002] GOA (gate on array, gate drive circuit substrate) is an important technology in panel design. The main advantage is that it can eliminate the gate drive integrated circuit and reduce product cost. The driver generates a clock signal and sends it to the gate drive circuit. The gate drive circuit provides a clock signal to each gate drive circuit through the clock signal line for row scanning. [0003] Since the clock signal line is responsible for providing signals to the gate drive circuit, of course, it is not expected that the signal will pass through these lines to cause signal attenuation. Generally, PSA (Polymer Sustained Alignment, Polymer Sustained Alignment) mode and VA (Vertical Alignment, vertical alignment) two In this mode, the signal resistan...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G02F1/1362
CPCG02F1/136286
Inventor 胡云钦
Owner HKC CORP LTD
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