Memory device addressing stress voltage

Abstract

A memory device addressing stress voltage includes at least one memory cell, a bit line, a protection circuit, and a write circuit including a write controller and a write driver. The write driver receives the output signal from the write controller and outputs it to the bit line. The protection circuit can effectively reduce at least the cross-voltage between the input terminal of the write driver and the ground terminal, so as to solve the problem that the stress voltage of the write driver is too high.

Description

technical field [0001] The present invention relates to a memory device for solving the stress voltage, in particular to a memory device for solving the stress voltage (Stress Voltage) problem of negative bit line (Negative Bit-line; NBL) technology. Background technique [0002] With the advancement of semiconductor manufacturing technology, the power supply voltage of the memory circuit is getting lower and lower, especially at the worst corner of the process, which makes the writing operation of the memory device difficult. Among them, in order to improve the voltage range of the writing operation of the memory device, an existing negative bit line (NBL) technology is proposed and widely used in various memory devices, such as static random access memory (SRAM), In order to solve the problem that the memory device is prone to data writing failure due to the most unfavorable manufacturing process corner. [0003] refer to figure 1 , figure 1 It is a schematic circuit di...

AI Technical Summary

Problems solved by technology

[0005] The object of the present invention is to provide a memory device that solves the problem of excessive stress voltage caused by using the existing negative bit line technology

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