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Flash memory wear balancing algorithm with low memory consumption

A wear-leveling and low-memory technology, applied in information storage, static memory, read-only memory, etc., can solve the problems of increasing the number of operation error bits and different erasing times, and achieve reduced consumption, effective static wear leveling algorithm, Judging the effect of accurate cold and hot data

Active Publication Date: 2019-03-26
SLICONGO MICROELECTRONICS INC
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  • Application Information

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Problems solved by technology

As the erasing times of solid state drives increase, the number of error bits in write (erase) operations fluctuates.
At the same time, when each block reaches the maximum number of error-correctable bits, the cumulative number of erasures is different, so it is not appropriate to simply use the number of erasures or the number of error bits to evaluate the status of a solid state drive

Method used

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  • Flash memory wear balancing algorithm with low memory consumption
  • Flash memory wear balancing algorithm with low memory consumption
  • Flash memory wear balancing algorithm with low memory consumption

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Embodiment 1

[0023] The SSD will be affected by the reading and writing of surrounding blocks during the reading and writing process, which will cause the actual erasable times of each block to be different. Moreover, when the solid-state hard disk leaves the factory, all the blocks can reach the maximum number of erasable times, and the maximum number of erasable times marked is only about one-third of the actual number. As the erasing times of solid-state hard drives increase, the number of error bits in write (erase) operations increases in a fluctuating manner. At the same time, when each block reaches the maximum number of error-correctable bits, the cumulative number of erasures is different, so it is not appropriate to simply use the number of times of erasure or the number of error bits to evaluate the status of a solid state drive. Such as figure 2 Shown is the relationship between the number of erasures and the number of error bits, image 3 Shown is the volatility of the numb...

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Abstract

The invention discloses a flash memory wear balancing algorithm with low memory consumption, At that same time, the data block with small error correction code number and high relative erase number are given more writing opportunities. The invention judges the hot and cold data more accurately, the static wear balance algorithm is more effective, and the solid-state hard disk can reach its true writing times life. The invention adopts the relative erase number and the error correction code number to decide the hot and cold data blocks.

Description

technical field [0001] The invention relates to the field of solid-state storage, and more specifically, to a wear leveling algorithm of flash memory with low memory consumption. Background technique [0002] The solid-state hard disk is composed of a main control unit and a solid-state storage unit (attached figure 1 ), the solid-state storage unit is composed of multiple NAND flash memory data blocks. Since the SSD does not have a rewriting mechanism, after a block is full of data, the data in the block needs to be erased before new data can be written. When the data is updated, rewrite the new data, mark the original data as invalid, and enter the state to be erased. [0003] The physical characteristics of solid-state drives determine that its rewritable times are limited. SLC has a write (erase) life of about 100,000 times, and MLC has a write (erase) life of about 3,000 to 10,000. The storage capacity has been doubled, and the write (erase) life is less than one-ten...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/34
CPCG11C16/3495
Inventor 陈弯弯韩国军方毅蔡国发朱增昌
Owner SLICONGO MICROELECTRONICS INC