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Fault Injection Attack Simulation Method for Integrated Circuits Based on Partial Scanning

A technology of fault injection and integrated circuits, applied in simulators, measuring electricity, measuring electrical variables, etc., to achieve the effect of reducing resource consumption and low resource consumption

Active Publication Date: 2020-12-11
TIANJIN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] Fault injection attack simulation method for integrated circuits based on full scan will bring huge logic overhead [4]

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  • Fault Injection Attack Simulation Method for Integrated Circuits Based on Partial Scanning
  • Fault Injection Attack Simulation Method for Integrated Circuits Based on Partial Scanning
  • Fault Injection Attack Simulation Method for Integrated Circuits Based on Partial Scanning

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Embodiment Construction

[0036] The present invention will be further described below through specific embodiments and accompanying drawings. The embodiments of the present invention are for better understanding of the present invention by those skilled in the art, and do not limit the present invention in any way.

[0037] The technical solution of the present invention is based on a partial scanning integrated circuit fault injection attack simulation method, such as figure 1 As shown, the specific steps are as follows:

[0038] Step 1, generating a circuit netlist by synthesizing the circuit to be tested;

[0039] Step 2, insert the scan chain in the circuit netlist;

[0040] Step 3, configure the hardware architecture composed of the netlist and the control module into the FPGA after integrated layout and routing;

[0041] Step 4, according to the netlist information, including: the scan chain length, the number of D flip-flop groups, and the basic input length of the circuit, generate a circui...

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Abstract

The invention discloses an integrated circuit fault injection attack simulation method based on partial scanning. The integrated circuit fault injection attack simulation method is used for achievingsimulation of fault injection attack of a partial scanning circuit using an FPGA, and mainly comprises the steps of preprocessing, setting, generation and injection simulation. The method achieves low-cost fault injection attack simulation based on a partial scanning method; fault injection attack is simulated by inserting a partial scanning chain in a netlist and adding a circuit control module and other fault injection logic; a control signal is transmitted from a PC to the FPGA through a PCIe port, and after the control signal is processed by the control module, fault injection is achieved.The method is high in simulation speed and low in logic cost.

Description

technical field [0001] The invention relates to the field of integrated circuit security, in particular to a partial scan-based integrated circuit fault injection attack simulation method. Background technique [0002] Fault injection attacks have become an effective way to attack chips [1] . Existing methods for evaluating the ability of integrated circuits to resist fault injection attacks mainly include chip testing [2-3] , hardware emulation [4-5] and software emulation [6-7] . Chip testing performs actual fault injection attacks on finished chips. The test efficiency is low and the cost is high. After a problem is found, the design modification cycle and cost are extremely high. In the design stage, it is necessary to evaluate the anti-fault injection attack capability of integrated circuits. The running speed of software simulation is slow, but the fault model space is large, the amount of fault data is large, and the simulation time is too long. Hardware simula...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/3185G05B17/02
CPCG01R31/318536G01R31/318544G01R31/318586G05B17/02
Inventor 李博超刘强
Owner TIANJIN UNIV