Semi-periodic capacitance proportional programmable band-gap reference circuit
A reference circuit and half-cycle technology, applied in the direction of adjusting electrical variables, control/regulation systems, instruments, etc., can solve the problems of large noise and large power consumption of bandgap reference circuits, and achieve reduced noise and power consumption, low power consumption , Solve the effect of large power consumption
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Embodiment 1
[0019] Embodiment 1, a half-period capacitance ratio programmable bandgap reference circuit
[0020] Such as figure 1 As shown, a half-period capacitance ratio programmable bandgap reference circuit provided by the present invention is composed of a start-up circuit 1 , a junction voltage generation circuit 2 , a sample-and-hold circuit 3 and a clock generation circuit 4 .
[0021] The start-up circuit 1 has two input terminals and two output terminals, and the two input terminals are connected to the external reset signal RS and the external restart signal RST respectively; The input terminals are connected; the junction voltage generating circuit 2 has four input terminals and two output terminals, wherein the two input terminals are respectively connected to the two output terminals of the start-up circuit 1, and the other two input terminals are connected to the external control signal P1 It is connected with P2; its two output terminals are respectively connected with t...
Embodiment 2
[0022] Embodiment 2, the implementation of the junction voltage generating circuit
[0023] Such as figure 2As shown, the junction voltage generating circuit 2 is composed of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP5, the first NMOS transistor MN1, the second NMOS transistor MN2, the first The transistor Q1, the second transistor Q2, the third transistor Q3, the first capacitor C1 and the second capacitor C2; wherein, the source of the first PMOS transistor MP1, the source of the second PMOS transistor MP2, and one end of the first capacitor C1 It is connected with one end of the second capacitor C2 and connected with the power supply VDD; the source of the third PMOS transistor MP3 is connected with the drain of the first PMOS transistor MP1; the source of the fourth PMOS transistor MP4 is connected with the drain of the second PMOS transistor MP2 The drains are connected; the gate of the firs...
Embodiment 3
[0024] Embodiment 3, implementation of sample and hold circuit
[0025] Such as image 3 As shown, the sample and hold circuit 3 is composed of a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a third capacitor C3, and a fourth capacitor C4 , the fifth capacitor C5 and an operational amplifier 5; wherein, the positive input node of the operational amplifier 5 is connected to one end of the third switch S3 and the fourth switch S4, and is connected to the second output signal Vbe2 of the junction voltage generating circuit; the operational amplifier The negative input node of 5 is connected to one end of the third capacitor C3 and the fourth capacitor C4 and the other end of the third switch S3; the output node of the operational amplifier 5 is connected to one end of the fifth switch S5 and the sixth switch S6; the first switch S1 crosses Connected to the common node connected to the third capacitor C3, the se...
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