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Semiconductor structures and methods of forming them

A technology of semiconductors and transistors, applied in the field of semiconductor structures and their formation, can solve problems such as the difficulty of metal silicide layers

Active Publication Date: 2021-02-05
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the metal silicide layer formed in the prior art is more difficult

Method used

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  • Semiconductor structures and methods of forming them
  • Semiconductor structures and methods of forming them
  • Semiconductor structures and methods of forming them

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Experimental program
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Embodiment Construction

[0024] As mentioned in the background art, it is very difficult to form the metal silicide layer.

[0025] Figures 1 to 2 It is a structural schematic diagram of each step of a method for forming a semiconductor structure.

[0026] Please refer to figure 1 , provide a substrate 100, the substrate 100 includes an NMOS region and a PMOS region connected to the NMOS region, the substrate 100 has a gate structure (not shown) extending from the NMOS region to the PMOS region; A first source-drain doped region 101 is formed in the PMOS region substrate 100 on both sides of the gate structure; a second source-drain doped region 102 is formed in the NMOS region substrate 100 on both sides of the gate structure; Form a dielectric layer 103 on the first source-drain doped region 101 and the second source-drain doped region 102, and on the sidewall and top surface of the gate structure; remove the first source-drain doped region 101 and the second source-drain doped region The dielec...

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Abstract

A semiconductor structure and a method for forming the same. The method includes: providing a base, the base includes a first region and a second region connected to the first region, and the first region and the second region respectively have a plurality of fins on the substrate; A first source-drain doped region is formed in the fin; a first protective layer is formed on the sidewall of the fin in the second region; a second source-drain doped region is formed in the fin of the second region, and the sidewall of the second source-drain doped region covers The first protective layer; forming a dielectric layer on the substrate, the dielectric layer has an opening extending from the first region to the second region, and the opening exposes the sidewall of the first protective layer, the top of the second source and drain doped region, and the first The sidewall and top of the source and drain doped regions; a first metal silicide layer is formed at the bottom of the opening; after the first metal silicide layer is formed, the first protective layer is removed; after the first protective layer is removed, a second source and drain are formed at the bottom of the opening The sidewall of the doped region forms a second metal silicide layer. The formed semiconductor device has good performance.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] Complementary metal-oxide-semiconductor (CMOS) transistors, as the most basic devices in semiconductor manufacturing, are often widely used in various integrated circuits. Complementary metal oxide semiconductors are divided into NMOS transistors and PMOS transistors according to the main carrier and the doping type during manufacture. The NMOS transistor includes: a first source-drain doping region, and the PMOS transistor includes a second source-drain doping region. [0003] In the existing CMOS process, in order to improve the contact resistance between the first source-drain doped region and the first conductive plug on the first source-drain doped region, and the second source-drain doped region and the second source The contact resistance of the second conductive plug on the d...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238H01L27/092
CPCH01L21/823814H01L27/092
Inventor ęŽå‹‡
Owner SEMICON MFG INT (SHANGHAI) CORP