Area efficient architecture for multi way read on highly associative content addressable memory (CAM) arrays

Abstract

Aspects disclosed herein relate to techniques and an efficient architecture for enabling multi-way reads on highly associative content addressable memory (CAM) arrays. For example, a method for performing a tag search of a tag array can include reading a first subset of stored tag bits from multiple entries of the tag array, and comparing a second subset of stored tag bits from a one or more entries of the tag array against a search-tag to produce one or more possible way hit signals.

Description

[0001] Cross References & Priority Claims to Related Applications [0002] This patent application claims the benefit of U.S. Provisional Patent Application No. 62 / 401,614, filed September 29, 2016, and U.S. Patent Application No. 15 / 710,108, filed September 20, 2017, both of which are assigned to the present assignee and is hereby expressly incorporated herein by reference. technical field [0003] Aspects disclosed herein relate to the field of memory architectures. More specifically, aspects disclosed herein relate to content addressable memory (CAM). Background technique [0004] Content-addressable memory (CAM) is a type of memory that enables high-speed parallel searches of the memory for desired data words. Thus, CAM can be used for search-intensive applications. [0005] In high-performance CPU architectures, the cache hit ratio is an important factor in the overall achievable instructions per cycle (IPC) of the architecture. Server CPU architectures typically h...

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Problems solved by technology

[0006] However, such compression typically adversely affects the power, performance, or area (PPA) of the tag array and incurs a timing penalty since the compressed bits may need to be looked up prior to the tag search.

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