auxiliary circuit of SRAM

Abstract

The embodiment of the invention discloses an auxiliary circuit of an SRAM. Memory cell array, The auxiliary circuit comprises a memory cell array, a word line and a clock signal line, the word line isconnected to the memory cell array and is suitable for responding to a clock signal of the clock signal line to generate a word line signal so as to select a memory cell in the memory cell array, andthe auxiliary circuit comprises a word line voltage reduction unit suitable for reducing the voltage value of the word line signal; and a word line voltage boosting unit coupled with the word line voltage reducing unit and suitable for reducing the reduction amount of the voltage value of the word line signal by the word line voltage reducing unit in response to the word line signal. The auxiliary circuit of the SRAM is high in read-write speed.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an auxiliary circuit of an SRAM. Background technique [0002] Memory is an indispensable and important part in the field of integrated circuit technology. Static Random Access Memory (SRAM), as a type of memory with a faster read and write speed, has always been a research hotspot in the field of integrated circuit technology. . [0003] SRAM is mainly used as a high-speed cache, which has high requirements for the read and write speed of SRAM. On the other hand, with the development of semiconductor technology, the feature size of devices is getting smaller and smaller, and the power supply voltage of SRAM is getting lower and lower. [0004] Due to the reduction of the feature size and the reduction of the power supply voltage of the SRAM, the static noise tolerance of the storage unit of the SRAM is reduced, which makes the SRAM prone to interference during oper...

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Problems solved by technology

[0005] However, the speed of SRAM with auxiliary circuits needs to be improved at present.

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