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Dynamic frequency boosting exploiting path delay variability in integrated circuits

A technology of circuit paths and combinational circuits, applied in electrical digital data processing, constraint-based CAD, special data processing applications, etc., can solve problems such as lack of automation tools, clock frequency depends on critical path delay, high design complexity, etc., to achieve The effect of improving system performance

Pending Publication Date: 2019-06-18
N 左姆帕奇斯
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

A disadvantage of synchronous designs is the fact that the clock frequency necessarily depends on the critical path delay
In the case of asynchronous designs, disadvantages include high design complexity, non-discrete time (asynchronous) operation, and lack of automated tools to support the design

Method used

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  • Dynamic frequency boosting exploiting path delay variability in integrated circuits
  • Dynamic frequency boosting exploiting path delay variability in integrated circuits
  • Dynamic frequency boosting exploiting path delay variability in integrated circuits

Examples

Experimental program
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Embodiment Construction

[0048] The following is a detailed description of the embodiments of the present invention. The descriptions refer to the foregoing figures to provide illustrative views of the invention. The scope is to teach and to provide clear indications regarding the application of the presented techniques and to address potential design issues. All modifications, adaptations or variations relying on the teachings of the present invention, where the teachings have advanced the art, are considered to be within the spirit and scope of the present invention. Accordingly, the description and drawings should not be considered in a limiting sense, but it is to be understood that the invention is by no means limited to the illustrated embodiments.

[0049] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "typical" is not necessarily to be construed as preferred or advantageous over other embodiments. It is to b...

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PUM

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Abstract

The disclosure is directed to the design and manufacture of synchronous digital systems, such as integrated circuits (IC), to employ dynamic frequency boosting. The proposed technique overcomes limitations of conventional synchronous clock design by boosting operating clock frequency despite critical path time constraints and without violating the correct functionality. In accordance with an exemplary embodiment, ICs are configured to set the clock frequency during each state event by selecting a more optimum clock frequency, on a clock cycle basis, thus improving system performance in terms of throughput while maintaining the benefits and design approach of synchronous digital systems.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to U.S. Nonprovisional Application No. 15 / 644,760, filed July 8, 2017, entitled "DYNAMIC FREQUENCY BOOSTING EXPLOITING PATH DELAY VARIABILITY IN INTEGRATED CIRCUITS," which U.S. Nonprovisional Application No. 15 / 644,760 claims Priority to U.S. Provisional Application No. 62 / 359,814, filed July 8, 2016, entitled "A DYNAMIC FREQUENCY BOOSTING METHOD EXPLOITING PATH DELAY VARIABILITYIN INTEGRATED CIRCUITS," both of which are hereby owned by the same assignee And accept. technical field [0003] The present invention relates to techniques for optimizing clock speeds in integrated circuits. Background technique [0004] Electronic design automation (EDA), also known as electronic computer-aided design (ECAD), is a class of software tools used to design electronic systems such as integrated circuits and printed circuit boards. These tools work together in the design flow that chip designers...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/324G06F1/08G06F17/50
CPCG06F1/08G06F1/3206G06F1/324G06F30/3312G06F30/327G06F30/398G06F30/394G06F2119/12Y02D10/00G06F2111/04G06F30/3315
Inventor N·左姆帕奇斯
Owner N 左姆帕奇斯