A data writing control circuit and a control method

Abstract

The invention provides a data writing control circuit and a control method. The data writing control circuit comprises a counter, a detector, a data latch module, a delay module, an encoder and a driver. The counter starts counting and generates an address after receiving the write-in data, and transmits the address to the detector; After the address reaches the maximum address, the detector outputs an overflow control signal to the encoder; After receiving the write-in data, the data latching module latches the write-in data and transmits the write-in data to the delay module; The delay module is used for delaying the data output by the data latching module and transmitting the delayed data to the encoder so as to synchronously transmit the data and the address; And after receiving the overflow control signal, the encoder recodes the delayed data, and rewrites the data of the overflow part into default data. Due to the fact that the default data are invalid data, the default data cannot be transmitted to the driver, overflow data can be prevented from covering original data, and power consumption can be reduced.

Description

technical field [0001] The present invention relates to the technical field of memory data processing, and more specifically, to a data writing control circuit and a control method. Background technique [0002] In the relevant scenarios of memory data writing, due to the limited input length of the data, it has the maximum address. Therefore, the externally provided address and the internally automatically counted address may exceed or reach the maximum address. At the same time, the external data It is still inputting, if it is not processed, the data beyond the addressing range will overwrite the original data. [0003] figure 1 It is a structural schematic diagram of an existing data writing control circuit. When the counter reaches the maximum address, the detector outputs an overflow control signal, and the driver is turned off through the overflow control signal, so that data beyond the addressing range cannot be written into the target memory. . However, in the da...

AI Technical Summary

Problems solved by technology

[0003] figure 1 It is a structural schematic diagram of an existing data writing control circuit. When the counter reaches the maximum address, the detector outputs an overflow control signal, and the driver is turned off through the overflow control signal, so that data beyond the addressing range cannot be written into the target memory.

However, in the data writing control circuit, the change of the data signal will always be transmitted to the input terminal of the driver, even if the driver does not write data, the power consumption is still high

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