High voltage semiconductor device having increased breakdown voltage and method of fabricating the same

Abstract

A high voltage semiconductor device and a method of fabricating the same are disclosed. The high voltage semiconductor device includes a semiconductor substrate, a gate structure, at least one first isolation structure, at least one second isolation structure, and at least one first drift region. The gate structure is disposed on the semiconductor substrate. The first isolation structure and the second isolation structure are disposed in an active region of the semiconductor substrate on one side of the gate structure. An end of the second isolation structure is disposed between the first isolation structure and the gate structure, and an end of the first isolation structure is disposed between the first doped region and the second isolation structure. The bottom of the at least one firstisolation structure and the bottom of the at least one second isolation structure are deeper than the bottom of the first drift region.

Description

[0001] field of invention [0002] The present invention relates to semiconductor devices and methods of manufacturing the same, and more particularly, to high-voltage semiconductor devices with increased breakdown voltage and methods of manufacturing the same. Background technique [0003] In a general metal-oxide-semiconductor (MOS) transistor, since the drain region overlaps the gate electrode, it is easy to occur at the overlapping region of the drain region and the gate electrode due to the influence of gate-induced drain leakage (GIDL) Electrical breakdown. In particular, in the application of peripheral circuits of flash memory, such as in 3D NAND flash memory, higher and higher erase voltages are required for triple-level cell (TLC) or quad-level cell (QLC), so for controlling TLC Or QLC MOS transistors require a higher breakdown voltage. [0004] In order to increase the breakdown voltage of MOS transistors, planar high voltage MOS transistors have been developed to...

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Problems solved by technology

However, these methods enlarge the top-view area of ​​MOS transistors, which limits the reduction in the size of devices with MOS transistors

Another method is to manufacture a gate oxide layer with a stepped shape to increase the thickness of the gate oxide layer between the gate electrode and the drain region, but this method requires additional masks and additional processes, which increases the manufacturing cost. cost

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