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Three-dimensional stacked packaging integrated TR module

A three-dimensional stacking and module technology, applied in electrical components, electrical solid-state devices, circuits, etc., can solve the problems of increased full-cycle cost, loop self-excitation, and decreased yield, and achieves sufficient functional expansion margin and installation projection. The effect of increased area and high space utilization

Active Publication Date: 2019-07-19
10TH RES INST OF CETC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] It is precisely because of the characteristics of the above-mentioned circuit structure that the 2.5D-SIP packaging solution has exposed many problems and deficiencies in its application: First, at the chip-level integration level, the multi-channel multi-functional heterogeneous assembly layout is limited to a two-dimensional plane, and the space utilization rate is limited. Not high, the improvement of the chip carrying function and the expansion of the size will directly lead to the increase of the volume of the entire package, especially the area of ​​the installation projection direction in the two-dimensional plane
The second is the SIP packaging level. Due to factors such as thermal stress matching and reliability in the later installation, the size of a single package cannot be increased indefinitely. Currently, 10*10mm is an empirical upper limit.
This will limit the improvement potential of the 2.5D-SIP solution in carrying functional density and integration density
Third, from the perspective of TR link gain distribution and space isolation, all chips are directly assembled in a single shell space, and multi-channel high-gain centralized layout makes it difficult to provide effective isolation of electromagnetic signals from the structural design, which can easily lead to loop Stability issues such as road self-excitation, and also limit the performance improvement and application of a single tube shell
Three-dimensional chip packaging stacks multiple dies to achieve high integration density, but such a complex packaging design will bring many problems: such as how to stack multiple chips in one package; and complex wiring A common carrier board is required, and it is difficult to lay out the wiring with traditional tools; especially for the stacking of active chips in the millimeter wave band, the effective isolation of electromagnetic signals will become more difficult; finally, the above-mentioned unfavorable factors will work together to lead to lower yields. Decrease and increase of whole cycle cost

Method used

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Embodiment Construction

[0018] refer to figure 1 with figure 2 . In the preferred embodiment described below, a three-dimensional stack package TR module includes: an upper multi-layer dielectric substrate 1 assembled in a Z-direction stack, a lower multi-layer dielectric substrate 2 and a metal layer that hermetically seals the upper multi-layer dielectric substrate 1 Cover plate 3, wherein: the upper multi-layer dielectric substrate 1 is made with an upper substrate rectangular open cavity embedded with integrated four-channel multifunctional digital-analog hybrid Corechip chip 4, and the two sides of the upper rectangular open cavity of the upper multi-layer dielectric substrate 1 are long There are five sets of microstrip interfaces 5 printed on the side parallel to the X direction and one wide side parallel to the Y direction, and on the printed circuit surface at the bottom of the upper multilayer dielectric substrate 1, there is a connection with the microstrip interface 5 on the upper subst...

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Abstract

The invention discloses a three-dimensional stacked and packaged TR module, and aims to provide a millimeter wave TR module which gives consideration to function expansion, space electromagnetic isolation and realizability. The invention is realized through the technical scheme that a method comprises the following steps: constructing an upper substrate rectangular open cavity in which an integrated four-channel multifunctional digital-analog hybrid chip is embedded in an upper multilayer dielectric substrate, printing microstrip interfaces on long edges of two sides in the Y direction and wide edges of one side in the X direction on steps in the cavity, and integrating a coaxial interface and a low-frequency interface, which are located on the bottom surface of the substrate, in the substrate at the same time. Rectangular open cavities for assembling the double-channel TR chips are constructed in the lower multilayer dielectric substrate, and two pairs of independently-extending lowersubstrate microstrip interfaces parallel to the X direction and coaxial interfaces correspondingly communicated with the lower substrate microstrip interfaces and fed to the top and the bottom of thelower multilayer dielectric substrate respectively are printed on steps in the cavities. High and low frequency signal interconnection and external feed-through of chips in an upper integrated spaceand a lower integrated space are achieved through alignment stacking of the upper substrate and the lower substrate and vertical interconnection holes and wires in the multilayer substrate.

Description

technical field [0001] The invention relates to a three-dimensional stacked package integrated TR implemented in the form of three-dimensional three-dimensional package integration (3D-SIP) and applied in the two-dimensional active phased array antenna of AIP (Antenna-In-Package), which works in the millimeter wave frequency band. mod. Background technique [0002] The millimeter-wave two-dimensional active phased array antenna has been rapidly developed and widely used in recent years because of its non-inertial agility of the scanning beam, excellent radio frequency performance, and good channel redundancy. According to the spread dimension of the active transceiver link function in the array architecture, the two-dimensional millimeter-wave active phased array antenna has successively formed two classic integrated architectures: brick (spread in Z direction) and tile (spread in X-Y plane). In the above architecture, the antenna radiation unit, TR component, beamforming n...

Claims

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Application Information

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IPC IPC(8): H01L23/538H01L23/552H01L25/16
CPCH01L23/5386H01L23/552H01L25/165
Inventor 张凯
Owner 10TH RES INST OF CETC
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