Digital clock frequency doubling circuit system and digital clock frequency doubling signal generation method

Abstract

The invention discloses a digital clock frequency doubling circuit system which comprises a duty ratio digital calibration circuit module and an OR gate circuit module. The duty ratio digital calibration circuit module comprises a pulse generator and a half-clock period delay circuit; an input clock signal passes through the duty ratio digital calibration circuit module and the OR gate circuit module to output a frequency-doubled output clock signal. In addition, the invention also discloses a digital clock frequency multiplication signal generation method. By adopting the digital clock frequency doubling circuit system based on 50% duty ratio calibration, the jitter of an output clock is effectively reduced, the power consumption and area of the circuit are saved, meanwhile, the responsetime between an input clock signal FIN and an output clock signal FOUT is shortened by 33%, and a high-speed response scene can be supported.

Description

technical field [0001] The invention relates to the technical field of digital circuits, in particular to a digital clock frequency multiplication circuit system and a digital clock frequency multiplication signal generation method. Background technique [0002] The digital clock multiplier circuit is a circuit module commonly used in integrated circuits such as Universal Asynchronous Receiver / Transmitter (UART for short) interface, Phase-locked loops (PLL for short) and the like. For the Universal Asynchronous Receiver Transmitter (UART) interface, the digital clock multiplier circuit can increase the transmission baud rate of the UART; and for the Phase Locked Loop (PLL) circuit, increase the digital clock multiplier on the input path of the reference clock The frequency circuit can make the crystal oscillator frequency supported by the phase-locked loop (PLL) more diverse, thereby improving the flexibility and reusability of the overall circuit system. [0003] In the pr...

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Problems solved by technology

[0007] However, the inventor found through research that although the digital clock frequency multiplication circuit system based on 50% duty cycle calibration in the prior art can realize the double frequency function, the circuit structure is still relatively complicated, especially Figure 5 , Image 6 , Figure 7 The circuit implementation shown has a large circuit area and dynamic power consumption and a long clock path

For the clock signal, each level of gate circuit on its path will accumulate phase noise, increase the jitter of the clock edge, and cause the deterioration of system performance

In order to reduce the clock jitter, the improvement method that can be adopted is to increase the gate width and gate length of the MOS transistors of the circuits at all levels on the clock path in equal proportions to reduce the flicker noise contribution, but this will increase the circuit area in a quadratic relationship; or increase each The drive capability of the stage circuit to suppress clock jitter, but the circuit power consumption will increase significantly

Therefore, the clock path of the digital clock multiplier circuit is too long will seriously deteriorate the clock jitter, while increasing the power consumption and area cost of the circuit

Secondly, since there is a delay of 1.5 input clock cycles between the input signal a and the output signal b of the half clock cycle delay circuit (HCDL), it determines the start-up time of the digital clock frequency multiplication circuit system, which is determined by the input clock The delay from the first edge of the signal FIN to the first edge of the output clock signal FOUT is 1.5 input clock cycles, such as Figure 4 As shown, the output clock signal FOUT needs to wait for 1.5 input clock cycles before it can be output normally, which is unacceptable for application scenarios that require high-speed response

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