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A stacked multi-chip qfn packaging method

A packaging method and multi-chip technology, applied in the manufacturing of electrical components, circuits, semiconductor/solid-state devices, etc., can solve the problems of high cost, difficult welding, and inability to use gold wires, and achieve low arc energy stress for long wires and reduce production. cost, the effect of improving reliability

Active Publication Date: 2021-07-30
池州华宇电子科技股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But as we all know, the thickness of the QFN product itself is only 0.75mm, while the thickness of the chip is 0.2mm, the superposition is 0.4mm, plus the thickness of 0.05mm of silver glue twice, and the height of the line arc is 0.2mm, the overall is 0.65mm, plus the laser The depth of the marking font is simply impossible to achieve
In addition, the welding between superimposed chips is more difficult. After all, if they are not on the same plane, there will be resonance, which will cause the rebound of the welding wire, especially the use of copper wire welding between two ICs is even more difficult, and the use of gold wire cost will be high

Method used

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  • A stacked multi-chip qfn packaging method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0028] Such as figure 1 Shown, a stacked multi-chip QFN packaging method, the packaging method comprises the following steps:

[0029] 1) Thinning scribing, first thinning the first chip wafer and the second chip wafer to a thickness of 150um through a grinder, and then cutting the first chip wafer into several single second chip wafers by a dicing machine One wafer is reserved, and the second chip wafer is cut by the following method for future use:

[0030] a) Heat up the lamination machine to 65°C;

[0031] b) Place the back of the second chip wafer upwards on the top of the workbench of the lamination machine;

[0032] c) Place the adhesive film on the back of the second chip wafer and extract the air between the adhesive film and the second chip wafer, then use a press to apply positive pressure vertically to the adhesive film to make the adhesive film and the second chip wafer Chip wafer bonding, the positive pressure is 0.4MPa, and the adhesive film includes an adhes...

Embodiment 2

[0045] Such as figure 1 Shown, a stacked multi-chip QFN packaging method, the packaging method comprises the following steps:

[0046] 1) Thinning scribing, first thinning the first chip wafer and the second chip wafer to a thickness of 150um through a grinder, and then cutting the first chip wafer into several single second chip wafers by a dicing machine One wafer is reserved, and the second chip wafer is cut by the following method for future use:

[0047] a) Heat up the lamination machine to 65°C;

[0048] b) Place the back of the second chip wafer upwards on the top of the workbench of the lamination machine;

[0049] c) Place the adhesive film on the back of the second chip wafer and extract the air between the adhesive film and the second chip wafer, then use a press to apply positive pressure vertically to the adhesive film to make the adhesive film and the second chip wafer Chip wafer bonding, the positive pressure is 0.5MPa, and the adhesive film includes an adhes...

Embodiment 3

[0062] Such as figure 1 Shown, a stacked multi-chip QFN packaging method, the packaging method comprises the following steps:

[0063] 1) Thinning scribing, first thinning the first chip wafer and the second chip wafer to a thickness of 150um through a grinder, and then cutting the first chip wafer into several single second chip wafers by a dicing machine One wafer is reserved, and the second chip wafer is cut by the following method for future use:

[0064] a) Heat up the lamination machine to 65°C;

[0065] b) Place the back of the second chip wafer upwards on the top of the workbench of the lamination machine;

[0066] c) Place the adhesive film on the back of the second chip wafer and extract the air between the adhesive film and the second chip wafer, then use a press to apply positive pressure vertically to the adhesive film to make the adhesive film and the second chip wafer Chip wafer bonding, the positive pressure is 0.45MPa, and the adhesive film includes an adhe...

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Abstract

The invention discloses a stacked multi-chip QFN packaging method, which replaces the traditional silver paste with a thickness of 0.05mm by setting an adhesive film with a thickness of 0.025mm, so that the overall height of the chip is reduced by 0.025mm. Using the reverse bonding method of 20um annealed copper wire, set the ball planting point with a maximum height of only 0.1mm on the top intermediate wafer, and use 20um annealed copper wire to lead from the side of the ball planting point to connect the intermediate wafer with the first Wafer connection reduces the overall height of the chip by 0.1mm, which meets the requirements of QFN packaging. At the same time, it can effectively increase the length of the arc connecting the intermediate wafer to the first wafer. The arc energy stress is low, which effectively improves the reliability of the connection; the conventional bonding method of 25um annealed copper wire can effectively reduce the production cost.

Description

technical field [0001] The invention relates to a packaging method, in particular to a stacked multi-chip QFN packaging method. Background technique [0002] With the development of the IC chip industry and the miniaturization trend of electronic products, the requirements for packaging products are getting higher and higher. Thinner products, smaller volumes, and multi-functions have become the mainstream. QFN products meet the above requirements, but most of the common products are single IC, or 2 IC chips, or multiple small IC chips are packaged on the same plane at the same time. If three ICs must be assembled in one product to achieve multi-functionality, but the chip area exceeds the product base plane or is very close to it, and cannot be placed flat, it is inevitable to think of stacked packaging. But as we all know, the thickness of the QFN product itself is only 0.75mm, while the thickness of the chip is 0.2mm, the superposition is 0.4mm, plus the thickness of 0.0...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/56H01L21/48
CPCH01L21/4821H01L21/561
Inventor 彭勇谢兵赵从寿韩彦召王钊周根强金郡唐振宁倪权张振林
Owner 池州华宇电子科技股份有限公司
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