Bitstream Graphical Method for Field Programmable Logic Gate Array Devices

Abstract

The invention discloses a bit stream imaging method of a field programmable logic gate array device, including imaging and automatic labeling; imaging: 1.1), removal of irrelevant information: locking data in the logic part of FPGA programmable logic In the CLB part, the rest of the information will not be considered in the process of bitstream imaging; 1.2), use the image recovery of a single CLB, and perform these single CLB recovery images according to the number of rows arranged in the two-dimensional array in the Device diagram Splicing to form the entire bitstream recovery map; automatic labeling: specify the range of resource areas used in the implementation process and the name of the bitstream output file. The present invention provides a brand-new algorithm that combines the two-dimensional physical distribution of FPGA logic resources, converts information used to describe configurable resources in bit streams into two-dimensional images with strong mapping relationships, and realizes automatic labeling of module functions.

Description

technical field [0001] The present invention relates to the field of field programmable logic gate array (FPGA, Field Programmable Gate Array) bit stream imaging field, and specifically proposes a bit stream programming logic configurable resource part imaging and automatic labeling combined with FPGA resource two-dimensional structure technology. Background technique [0002] Field programmable logic gate arrays have become one of the most widely used advanced digital systems over the past two decades. The big reason lies in the flexibility of FPGA products, mainly because FPGA can use the bit stream to reconfigure the internal logic. [0003] The FPGA bitstream configures the internal configurable resources of the FPGA, including the Configurable Logic Block (CLB), the Input / Output Block (IOB), the block memory (BRAM), etc. Property, IP) to update or add a new IP core, so as to achieve quick replacement. Obtaining information from the FPGA bit stream is generally divide...

AI Technical Summary

Problems solved by technology

One is that the size of the picture is too large; the other is that the mapping relationship between the image and the device is insufficient, that is, the correlation with the structure of the FPGA device cannot be shown

The reason for problem 1 is that the bit stream configured by the FPGA is too large. The size of the bit stream generated by the same series of FPGAs is fixed. For example, the fixed size of the bit stream generated by XilinxZYNQ-7000 702FPGA is 3.85M bytes. (ie 3,951K bytes)

All these data are used to generate images without loss, which will cause the image pixel size to reach more than 2000×2000 orders of magnitude, which will lead to extremely slow running speed during machine learning training; The content of the logic block (CLB) only accounts for 60% of the total data volume, and the resources used by the actual FPGA implementation algorithm are even less, so there are a large amount of data in the bit stream that has nothing to do with resource configuration, resulting in The image size is too large

As for the second problem, on the one hand, it is due to the influence of the above-mentioned large amount of irrelevant data, and on the other hand, due to the lack of a reasonable image algorithm that fully combines the bit stream structure and the distribution of FPGA physical resources, it is impossible to convert the bit stream into a picture. Intuitive and clear image

Images