CMOS inverter

Abstract

The invention discloses a CMOS phase inverter, which comprises an NMOS (N-channel Metal Oxide Semiconductor) transistor and a PMOS (P-channel Metal Oxide Semiconductor) transistor, wherein the NMOS transistor includes a first nanowire or nanosheet, and the PMOS transistor includes a second nanowires or nanosheet; the first and second nanowires or nanosheets are arranged in a direction perpendicular to the surface of a semiconductor substrate and aligned with each other; a channel region of the NMOS transistor is formed in the first nanowire or nanosheet, and a first gate dielectric layer is formed on the periphery of the channel region of the NMOS transistor; a channel region of the PMOS transistor is formed in the second nanowire or nanosheet, and a second gate dielectric layer is formedat the periphery of the channel region of the PMOS transistor; and the NMOS transistor and the PMOS transistor share a metal gate, and the metal gate is formed on the surfaces of the first gate dielectric layer and the second gate dielectric layer. The CMOS inverter can save the device area and reduce the cost.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a CMOS inverter. Background technique [0002] Such as figure 1 As shown, the circuit diagram of the CMOS inverter, the CMOS inverter 101 includes an NMOS transistor 103 and a PMOS transistor 102, the gate of the NMOS transistor 103 and the gate of the PMOS transistor 102 are connected together as a signal input terminal In, and the NMOS transistor 103 The drain of the PMOS transistor 102 and the drain of the PMOS transistor 102 are connected together as the signal output terminal Out, and the signals of the signal input terminal In and the signal output terminal Out are inverted. The source of the PMOS transistor 102 is connected to the power supply voltage Vcc, and the source of the NMOS transistor 103 is grounded to Gnd. [0003] Since the CMOS inverter 101 is mainly composed of an NMOS transistor 103 and a PMOS transistor 102 , the prior art adopts a structure in which ...

AI Technical Summary

Problems solved by technology

[0023] Depend on image 3 It can be seen from the above that although the NMOS transistor and PMOS transistor of the existing CMOS inverter adopt the GAA structure, it can be applied to a process node below 5nm, but due to figure 2 It can be seen from the figure that the NMOS tubes and PMOS tubes are distributed and arranged on the same plane, which will occupy a large area

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