Method and device for optimizing sub-threshold digital sequential circuit

Abstract

The embodiment of the invention discloses a method and a device for optimizing a sub-threshold digital sequential circuit. The method comprises: firstly, dividing a digital sequential circuit into a plurality of sub-modules; each sub-module being composed of a trigger and a front-end combinational logic circuit of the trigger; and then, according to the clock signal frequency of the sub-module, determining a delay constraint condition of the sub-module, determining a delay constraint condition of the sub-module, and then, optimizing the corresponding sub-module by taking the delay constraint condition of the sub-module as a constraint, thereby finishing optimization of the whole digital time sequence circuit. In the method, according to the requirements of specific circuits in each sub-module, the respective delay constraint conditions of the sub-modules are determined, and during the optimization, the optimization of the sub-modules can be performed by using the respective delay constraint conditions of the sub-modules as the constraints, such that the constraint conditions are accurate so as to reduce the optimization scale, and the optimization of the sub-threshold digital timesequence circuit is achieved through the local rapid optimization so as to accelerate the optimization speed.

Description

technical field [0001] The invention relates to the field of integrated circuit design automation (EDA), in particular to an optimization method and device for a sub-threshold sequential circuit. Background technique [0002] Subthreshold digital circuits refer to digital logic circuits whose operating voltage is lower than the threshold voltage of transistor devices. Since the circuit operates in the subthreshold region, the dynamic power consumption and static power consumption of the circuit can be greatly reduced. [0003] It is precisely because the device works in the sub-threshold region that the current and voltage of the device have an exponential relationship, and changes in the size of the device will cause significant changes in current and parasitic capacitance, thereby significantly changing the electrical performance of the circuit. In addition, the circuit performance fluctuates greatly with the change of PVT (Process Voltage Temperature, process temperature ...

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Problems solved by technology

This exponentially increases the complexity of device size optimization for subthreshold digital circuits, making the device optimization speed process extremely slow

As the scale of sub-threshold digital circuits increases, the combination of statistical analysis and optimization considering PVT deviations with traditional stochastic optimization algorithms and heuristic optimization algorithms cannot be directly applied to the optimization of large-scale sub-threshold digital circuits, especially It cannot be directly applied to the optimization of large-scale sub-threshold digital sequential circuits

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