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Method for manufacturing gate of trench gate power device

A technology of power devices and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems affecting the uniformity of the chip, affecting the ion implantation junction depth, and the depth of polysilicon. Effect of Intra-chip Uniformity

Inactive Publication Date: 2019-11-15
ZHUZHOU CRRC TIMES SEMICON CO LTD
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Problems solved by technology

[0004] However, when the polysilicon in the trench removes the polysilicon on the surface of the material and retains the polysilicon in the trench, the depth of the polysilicon in the trench will be different (such as Figure 5 shown), thus affecting the junction depth of subsequent ion implantation, and finally affecting the on-chip uniformity of device parameters such as threshold voltage

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  • Method for manufacturing gate of trench gate power device
  • Method for manufacturing gate of trench gate power device
  • Method for manufacturing gate of trench gate power device

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Embodiment Construction

[0030] The present invention will be further described below in conjunction with the drawings. In this way, the realization process of how to apply technical means to solve technical problems and achieve technical effects of the present invention can be fully understood and implemented accordingly. It should be noted that, as long as there is no conflict, the various technical features mentioned in the various embodiments can be combined in any manner. The present invention is not limited to the specific embodiments disclosed in the text, but includes all technical solutions falling within the scope of the claims.

[0031] Such as figure 1 Shown is a flowchart of a method for fabricating a trench gate power device gate of the present invention, Figure 2 to Figure 4 The morphology of the polysilicon after deposition, the morphology of the polysilicon after being fully oxidized, and the morphology of the polysilicon after etching are respectively shown; the details are as follow...

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Abstract

The invention relates to a method for manufacturing the gate of a trench gate power device. The method comprises the steps that 1 a semiconductor substrate is provided; 2 a trench is etched on the semiconductor substrate; 3 a gate oxide layer is formed on the upper surface of the semiconductor substrate and the inner wall of the trench; 4 the gate material is deposited on the upper surface of thesemiconductor substrate and fills the trench; 5 the gate material is oxidized, and an oxide gate material layer is formed; and 6 the oxide gate material layer is etched. According to the invention, ahigh-temperature furnace tube oxidation process is used to generate a polysilicon oxide layer with uniform thickness by oxidizing polysilicon on the upper surface of the semiconductor substrate; the high etching selectivity ratio of the polysilicon oxide layer to polysilicon is used; the polysilicon oxide layer is etched through a dry method or a wet method to form polysilicon with uniform depth in the trench to form a complete gate structure; and the in-chip uniformity of device parameters such as threshold voltage is improved.

Description

Technical field [0001] The invention belongs to the technical field of semiconductor manufacturing, and specifically relates to a method for manufacturing a trench gate power device gate. Background technique [0002] Power devices can be divided into power IC (integrated circuit) devices and power discrete devices. Power discrete devices include power MOSFET (metal-oxide semiconductor field effect transistor), high-power transistors and IGBT (insulated gate bipolar transistor) And other devices. Early power devices were produced based on planar technology, but with the development of semiconductor technology, small size, high power, and high performance have become the main development trends. Take the planar process MOSFET device as an example. Due to the limitation of the JFET (junction field effect transistor) parasitic resistance in its body, the area of ​​a single cell is limited, which makes it difficult to increase the cell density, and it is difficult to make the plane ...

Claims

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Application Information

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IPC IPC(8): H01L21/28
CPCH01L21/28035
Inventor 姚尧罗海辉肖强
Owner ZHUZHOU CRRC TIMES SEMICON CO LTD